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223. Memstor, memstance simulations via a versatile 4-port built with new adder and subtractor circuits.

Author

Minaei, Shahram, Göknar, Izzet Cem, Yıldız, Merih, and Yuce, Erkan

Subjects
*SIMULATION methods & models, *ELECTRIC potential, *METAL oxide semiconductors, *ELECTRIC impedance, *ELECTRIC circuits, *ELECTRIC inductance
Abstract

In this paper, novel voltage-mode (VM) n-channel metal-oxide semiconductor (NMOS) transistor-based analogue adder and subtractor circuits, which, respectively, performV1+V2andV1−V2operations, are presented. The most important feature of the proposed circuits is their extremely simple structures containing only six NMOS transistors. Further, the presented adder and subtractor circuits have high input and low output impedances, resulting in easy cascadability. The post-layout simulations of the proposed circuits have been executed using TSMC 0.25 µm process parameters with ±1.25 V. The area of the suggested circuits is approximately 30 × 13 µm2. Moreover, the topology of a generalised mutator, a versatile 4-port built with an adder and a subtractor, which acts as an ordinary mutator when properly reduced to a 2-port, is offered. A table for simulating lossless inductance, memristor, meminductor, memcapacitor and other elements under suitable termination of the 4-port is given, and three of these elements’ simulations with SPICE are also presented. [ABSTRACT FROM AUTHOR]

Published
2015
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224. A compact rail-to-rail CMOS buffer amplifier with very low quiescent current.

Author

Arslan, Emre, Yıldız, Merih, and Minaei, Shahram

Subjects
LIQUID crystal displays, ELECTRONIC amplifiers, TRANSISTORS, ELECTRIC circuits, ELECTRIC potential, COMPARATIVE studies
Abstract

In this work, a very compact, rail-to-rail, high-speed buffer amplifier for liquid crystal display (LCD) applications is proposed. Compared to other buffer amplifiers, the proposed circuit has a very simple architecture, occupies a small number of transistors and also has a large driving capacity with very low quiescent current. It is composed of two complementary differential input stages to provide rail-to-rail driving capacity. The push–pull transistors are directly connected to the differential input stage, and the output is taken from an inverter. The proposed buffer circuit is laid out using Mentor Graphics IC Station layout editor using AMS 0.35 μm process parameters. It is shown by post-layout simulations that the proposed buffer can drive a 1 nF capacitive load within a small settling time under a full voltage swing, while drawing only 1.6 μA quiescent current from a 3.3 V power supply. [ABSTRACT FROM AUTHOR]

Published
2015
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