565 results on '"Tahoori, Mehdi B."'
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202. Opportunistic write for fast and reliable STT-MRAM
203. Recovery-aware proactive TSV repair for electromigration in 3D ICs
204. Bias Temperature Instability Mitigation via Adaptive Cache Size Management
205. Leveraging aging effect to improve SRAM-based true random number generators
206. Electrolyte-Gated FETs Based on Oxide Semiconductors: Fabrication and Modeling
207. Workload-aware static aging monitoring of timing-critical flip-flops
208. Analysis of transient voltage fluctuations in FPGAs
209. Multicast Test Architecture and Test Scheduling for Interposer-Based 2.5D ICs
210. Runtime Adjustment of IoT System-on-Chips for Minimum Energy Operation.
211. Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales
212. Hold-time violation analysis and fixing in near-threshold region
213. Maximizing Energy Efficiency in NTC by Variation-Aware Microprocessor Pipeline Optimization
214. Improving Write Performance for STT-MRAM
215. Revisiting software-based soft error mitigation techniques via accurate error generation and propagation models
216. Fault injection acceleration by simultaneous injection of non-interacting faults
217. Invited - Cross-layer approaches for soft error modeling and mitigation
218. Low-Power Multi-Port Memory Architecture based on Spin Orbit Torque Magnetic Devices
219. Area-energy tradeoffs of logic wear-leveling for BTI-induced aging
220. Self-Timed Read and Write Operations in STT-MRAM
221. On-Chip Droop-Induced Circuit Delay Prediction Based on Support-Vector Machines
222. Online soft-error vulnerability estimation for memory arrays
223. Architecting STT Last-Level-Cache for performance and energy improvement
224. Layout-Based Modeling and Mitigation of Multiple Event Transients
225. Instruction cache aging mitigation through Instruction Set Encoding
226. Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames
227. Reliability-Aware Resource Allocation and Binding in High-Level Synthesis
228. Non-Volatile Non-Shadow flip-flop using Spin Orbit Torque for efficient normally-off computing
229. Error Propagation Aware Timing Relaxation For Approximate Near Threshold Computing.
230. Exploiting Instruction Set Encoding for Aging-Aware Microprocessor Design
231. Defect clustering-aware spare-TSV allocation for 3D ICs
232. Fine-grained aging prediction based on the monitoring of run-time stress using DfT infrastructure
233. Comprehensive Analysis of Sequential and Combinational Soft Errors in an Embedded Processor
234. Stepped parity: A low-cost multiple bit upset detection technique
235. Cross-layer approaches for an aging-aware design of nanoscale microprocessors: Dissertation summary: IEEE TTTC E.J. McCluskey doctoral thesis award competition finalist
236. Fault injection acceleration by architectural importance sampling
237. Towards a Hierarchical and Scalable Approach for Modeling the Effects of SETs
238. Energy efficient partitioning of dynamic reconfigurable MRAM-FPGAs
239. Extending standard cell library for aging mitigation
240. Self-awareness and self-learning for resiliency in real-time systems
241. Aging- and Variation-Aware Delay Monitoring Using Representative Critical Path Selection
242. Application-aware cross-layer reliability analysis and optimization
243. Deadspace-aware Power/Ground TSV planning in 3D floorplanning
244. Cross-layer resilient system design flow
245. Aging guardband reduction through selective flip-flop optimization
246. Reliability-aware operation chaining in high level synthesis
247. Re-using BIST for circuit aging monitoring
248. Protecting caches against multi-bit errors using embedded erasure coding
249. Resiliency challenges in sub-10nm technologies
250. Analysis and optimization of flip-flops under process and runtime variations
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