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[EN] Pure aluminium and aluminium alloy 1100 samples were anodized by one step and two step process. The foils were anodised in 0.3 M sulphuric acid solution at constant voltage of 25V and the temperature was maintained at 20 oC. The effect of increase of exposure time in second anodization step on the structural features was studied on AA 1100. A well ordered nanoporous structure were produced. It was found that in two step anodization process the produced film have very regular hexagonal cells with uniform pores as compare to single step anodization in both Al and AA 1100. The two step anodization improves both pore diameter and uniformity. With the increase in second step anodization time the complexities of porous film increases due to formation of sub pores.

Direct interfacing of nanosensors onto biomaterials could impact health quality monitoring and adaptive threat detection. Graphene is capable of highly sensitive analyte detection due to its nanoscale nature. Here we show that graphene can be printed onto water-soluble silk. This in turn permits intimate biotransfer of graphene nanosensors onto biomaterials, including tooth enamel. The result is a fully biointerfaced sensing platform, which can be tuned to detect target analytes. For example, via self-assembly of antimicrobial peptides onto graphene, we show bioselective detection of bacteria at single-cell levels. Incorporation of a resonant coil eliminates the need for onboard power and external connections. Combining these elements yields two-tiered interfacing of peptide-graphene nanosensors with biomaterials. In particular, we demonstrate integration onto a tooth for remote monitoring of respiration and bacteria detection in saliva. Overall, this strategy of interfacing graphene nanosensors with biomaterials represents a versatile approach for ubiquitous detection of biochemical targets., Published in the Journal of Nature Communications, v3 n763 p1-8, 2012. Supported in part by the Air Force Office of Scientific Research.

Direct interfacing of nanosensors onto biomaterials could impact health quality monitoring and adaptive threat detection. Graphene is capable of highly sensitive analyte detection due to its nanoscale nature. Here we show that graphene can be printed onto water-soluble silk. This in turn permits intimate biotransfer of graphene nanosensors onto biomaterials, including tooth enamel. The result is a fully biointerfaced sensing platform, which can be tuned to detect target analytes. For example, via self-assembly of antimicrobial peptides onto graphene, we show bioselective detection of bacteria at single-cell levels. Incorporation of a resonant coil eliminates the need for onboard power and external connections. Combining these elements yields two-tiered interfacing of peptide?graphene nanosensors with biomaterials. In particular, we demonstrate integration onto a tooth for remote monitoring of respiration and bacteria detection in saliva. Overall, this strategy of interfacing graphene nanosensors with biomaterials represents a versatile approach for ubiquitous detection of biochemical targets., Published in the Journal of Nature Communications, v3 n763 p1-8, 2012. Supported in part by the Air Force Office of Scientific Research.

Energy efficiency of electronic circuits is a critical concern in a wide range of applications from mobile multi-media to biomedical monitoring. An added challenge is that many of these applications have dynamic workloads. To reduce the energy consumption under these variable computation requirements, the underlying circuits must function efficiently over a wide range of supply voltages. This paper presents voltage-scalable circuits such as logic cells, SRAMs, ADCs, and dc-dc converters. Using these circuits as building blocks, two different applications are highlighted. First, we describe an H.264/AVC video decoder that efficiently scales between QCIF and 1080p resolutions, using a supply voltage varying from 0.5 V to 0.85 V. Second, we describe a 0.3 V 16-bit micro-controller with on-chip SRAM, where the supply voltage is generated efficiently by an integrated dc-dc converter., Natural Sciences and Engineering Research Council of Canada (NSERC), Texas Instruments Incorporated (Texas Instruments Graduate Women’s Fellowship for Leadership in Microelectronics), Intel Corporation (Intel Ph.D. Fellowship Program), Texas Instruments Incorporated, Nokia Corporation, Semiconductor Research Corporation . Focus Center for Circuit and System Solutions (C2S2), United States. Defense Advanced Research Projects Agency

This paper presents a low-power SoC that performs EEG acquisition and feature extraction required for continuous detection of seizure onset in epilepsy patients. The SoC corresponds to one EEG channel, and, depending on the patient, up to 18 channels may be worn to detect seizures as part of a chronic treatment system. The SoC integrates an instrumentation amplifier, ADC, and digital processor that streams features-vectors to a central device where seizure detection is performed via a machine-learning classifier. The instrumentation-amplifier uses chopper-stabilization in a topology that achieves high input-impedance and rejects large electrode-offsets while operating at 1 V; the ADC employs power-gating for low energy-per-conversion while using static-biasing for comparator precision; the EEG feature extraction processor employs low-power hardware whose parameters are determined through validation via patient data. The integration of sensing and local processing lowers system power by 14à by reducing the rate of wireless EEG data transmission. Feature vectors are derived at a rate of 0.5 Hz, and the complete one-channel SoC operates from a 1 V supply, consuming 9 ¿ J per feature vector.

8T bit-cells hold great promise for overcoming device variability in deeply scaled SRAMs and enabling aggressive voltage scaling for ultra-low-power. This paper presents an array architecture and circuits with minimal area overhead to allow column-interleaving while eliminating the half-select problem. This enables sense-amplifier sharing and soft-error immunity. A reference selection loop is designed and implemented in the column circuitry. By choosing one of the two reference voltages for each sense-amplifier in a pseudo-differential scheme, selection loop effectively reduces input offset. 8T test array fabricated in 45nm CMOS achieves functionality from 1.1V to below 0.5V. Test chip operates at 450MHz at 1.1V and 5.8MHz at 0.5V while consuming 12.9 mW and 46 μW [mu W] respectively., United States. Defense Advanced Research Projects Agency

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009., Cataloged from PDF version of thesis., Includes bibliographical references (p. 163-181)., Embedded SRAMs are a critical component in modern digital systems, and their role is preferentially increasing. As a result, SRAMs strongly impact the overall power, performance, and area, and, in order to manage these severely constrained trade-offs, they must be specially designed for target applications. Highly energy-constrained systems (e.g. implantable biomedical devices, multimedia handsets, etc.) are an important class of applications driving ultra-low-power SRAMs. This thesis analyzes the energy of an SRAM sub-array. Since supply- and threshold-voltage have a strong effect, targets for these are established in order to optimize energy. Despite the heavy emphasis on leakage-energy, analysis of a high-density 256x256 sub-array in 45nm LP CMOS points to two necessary optimizations: (1) aggressive supply-voltage reduction (in addition to Vt elevation), and (2) performance enhancement. Important SRAM metrics, including read/write/hold-margin and read-current, are also investigated to identify trade-offs of these optimizations. Based on the need to lower supply-voltage, a 0.35V 256kb SRAM is demonstrated in 65nm LP CMOS. It uses an 8T bit-cell with peripheral circuit-assists to improve write-margin and bit-line leakage. Additionally, redundancy, to manage the increasing impact of variability in the periphery, is proposed to improve the area-offset trade-off of sense-amplifiers, demonstrating promise for highly advanced technology nodes. Based on the need to improve performance, which is limited by density constraints, a 64kb SRAM, using an offset-compensating sense-amplifier, is demonstrated in 45nm LP CMOS with high-density 0.25[mu]m2 bit-cells., (cont.) The sense-amplifier is regenerative, but non -strobed, overcoming timing uncertainties limiting performance, and it is single-ended, for compatibility with 8T cells. Compared to a conventional strobed sense-amplifier, it achieves 34% improvement in worst-case access-time and 4x improvement in the standard deviation of the access-time., by Naveen Verma., Ph.D.

Aggressive supply voltage scaling to below the device threshold voltage provides significant energy and leakage power reduction in logic and SRAM circuits. Consequently, it is a compelling strategy for energy-constrained systems with relaxed performance requirements. However, effects of process variation become more prominent at low voltages, particularly in deeply scaled technologies. This paper presents a 65 nm system-on-a-chip which demonstrates techniques to mitigate variation, enabling sub-threshold operation down to 300 mV. A 16-bit microcontroller core is designed with a custom sub-threshold cell library and timing methodology to address output voltage failures and propagation delays in logic gates. A 128 kb SRAM employs an 8 T bit-cell to ensure read stability, and peripheral assist circuitry to allow sub-Vt reading and writing. The logic and SRAM function in the range of 300 mV to 600 mV, consume 27.2 pJ/cycle at the optimal V [subscript DD] of 500 mV, and 1 muW standby power at 300 mV. To supply variable voltages at these low power levels, a switched capacitor DC-DC converter is integrated on-chip and achieves above 75% efficiency while delivering between 10 muW to 250 muW of load power., Defense Advanced Research Projects Agency

Continuous on-scalp EEG monitoring provides a non-invasive means to detect the onset of seizures in epilepsy patients, but cables from the scalp pose a severe strangulation hazard during convulsions. Since the power of transmitting the EEG wirelessly is prohibitive, a complete SoC is presented, performing lowpower EEG acquisition, digitization, and local digital-processing to extract detection features, reducing the transmission-rate by 43x. To maximize power-efficiency, the acquisition LNA operates at the lowest reported VDD (of 1V, drawing 3.5muW), but is able to reject offsets (characteristic of metal-electrodes) that are even larger than the supply voltage. Importantly, its topology simultaneously optimizes noise-efficiency and input-impedance to maximize electrode signal-integrity, and it uses switch-capacitor transformers to improve the noise and manufactureabilty of large on-chip resistors. The complete SoC generates EEG featurevectors every 2sec, consuming a total of 9muJ per feature-vector., Intel Foundation (Ph.D. Fellowship Program), Natural Sciences and Engineering Research Council of Canada, Massachusetts Institute of Technology. Center for Integrated Circuits and Systems, National Science Council of Taiwan

In modern ICs, the trend of integrating more on-chip memories on a die has led SRAMs to account for a large fraction of total area and energy of a chip. Therefore, designing memories with dynamic voltage scaling (DVS) capability is important since significant active as well as leakage power savings can be achieved by voltage scaling. However, optimizing circuit operation over a large voltage range is not trivial due to conflicting trade-offs of low-voltage (moderate and weak inversion) and high-voltage (strong inversion) transistor characteristics. Specifically, low-voltage operation requires various assist circuits for functionality which might severely impact high-voltage performance. Reconfigurable assist circuits provide the necessary adaptability for circuits to adjust themselves to the requirements of the voltage range that they are operating in. This paper presents a 64 kb reconfigurable SRAM fabricated in 65 nm low-power CMOS process operating from 250 mV to 1.2 V. This wide supply range was enabled by a combination of circuits optimized for both subthreshold and above-threshold regimes and by employing hardware reconfigurability. Three different write-assist schemes can be selectively enabled to provide write functionality down to very low voltage levels while preventing excessive power overhead. Two different sense-amplifiers are implemented to minimize sensing delay over a large voltage range. A prototype test chip is tested to be operational at 20 kHz with 250 mV supply and 200 MHz with 1.2 V supply. Over this range leakage power scales by more than 50 X and a minimum energy point is achieved at 0.4 V with less than 0.1 pJ/bit/access., Defence Advanced Research Projects Agency