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Windowing techniques have been widely used for preprocessing of samples before fast Fourier transform (FFT) in real time spectral analysis to minimize spectral leakage and picket fence effect. Among all popular window functions, Kaiser-Bessel window is an obvious choice for its better spectral characteristics. In this paper, CORDIC (CO-ordinate Rotation DIgital Computer) based VLSI architecture for implementing Kaiser-Bessel window has been proposed for real time applications. The parallel-pipelined technique has been adopted for the present design to ensure high throughput. Various architectural design and implementation issues have been discussed. The physical synthesis for ASIC implementation of proposed architecture using Synopsys design compiler(Design Vision) and commercially available 0. 18 μm CMOS yields the core area of 52 mmand worst case dynamic power of 890 mW at an operating frequency and voltage of 400 MHz and 1.8 V respectively. [ABSTRACT FROM AUTHOR]

Abstract: This paper proposes hardware architecture of WiMAX OFDMA frequency domain processing system. The system mainly consists of channel estimator, equalizer, and subcarrier de-allocator. The system is optimized for flexible and re-configurable WiMAX OFDMA receiver. The flexibility feature is obtained by employing flexible control unit approach using task FIFO. Using this scheme, the designed system can handle various and complex data structure within OFDMA frame. The propesed architecture has been implemented in 0.13μm CMOS technology. The implementation result shows that chip area is about 0.45 mm2 and able to work in targeted system clock 54MHz. [Copyright &y& Elsevier]

In this brief, we propose a high-throughput layered decoder architecture to support a broader family of quasicyclic low-density parity-check (QC-LDPC) codes, whose parity-check matrices are constructed from arrays of circulant submatrices. Each nonzero circulant submatrix is a superposition of K cyclic-shifted identity matrices, where the circulant weight K\geq 1. We propose a novel layered decoder architecture to support QC-LDPC codes with any circulant weight. We present a block-serial decoding architecture which processes a layer of a parity check matrix block by block, where each block is a Z\times Z circulant matrix with a circulant weight of K. In the case study, we demonstrate an LDPC decoder design for the China Mobile Multimedia Broadcasting (CMMB) standard, which was synthesized for a TSMC 65-nm CMOS technology. With a core area of 3.9 mm^2, the CMMB LDPC decoder achieves a maximum throughput of 1.1 Gb/s with 15 iterations. [ABSTRACT FROM PUBLISHER]

Achieving good detection performance while incurring low complexity is known to be one of the major challenges in multiple-input multiple-output (MIMO) communications based on spatial multiplexing. The tuple search detector (TSD) was recently introduced, improving this trade-off with regard to other tree-search-based algorithms (e.g. single tree search or list sphere detector). Motivated by the tremendous gain achievable through the turbo principle and based on a previously developed soft-output (SO) TSD implementation, this work presents the first soft-input soft-output (SISO) TSD realization, scalable in constellation size and number of antennas and mapped to a highly parallel and pipelined VLSI architecture. The proposed SISO-TSD VLSI realization is instantiated for 4 × 4 MIMO transmission and 64-QAM constellation in 65-nm CMOS technology. For a given BER↔complexity trade-off, the throughput ranges from 57.3 Mbps (iterative detection-decoding with 3 iterations) to 403.6 Mbps (non-iterative detection-decoding) at a clock frequency of 454 MHz. The BER↔complexity trade-off can be moreover adjusted according to transmission conditions, reaching >1 Gbps in high SNR scenarios. A silicon area of 0.14 mm (97.7 kGEs) is occupied by the SISO-TSD core, reporting low power dissipation (58.2 mW - 73.9 mW) under typical case operating conditions. The proposed detector implementation achieves hence high throughput with reasonable hardware complexity, representing a very competitive strategy with regard to relevant state-of-the-art realizations. [ABSTRACT FROM AUTHOR]

Algebraic soft-decision (ASD) decoding algorithm of Reed-Solomon (RS) codes can achieve better performance-complexity tradeoff than other soft-decision decoding algorithms. The interpolation is a major step of ASD algorithms. In the case that multiple test vectors are involved, the interpolation needs to be carried out for each vector and leads to very high hardware complexity. To enable the sharing of computation results in the interpolation for different vectors, a backward interpolation scheme was developed previously to eliminate points from a given interpolation result, which is a Grobner basis. However, this scheme can only eliminate all points in the same code position when their multiplicities are all one and the number of points is one less than the number of polynomials in the Grobner basis. Larger multiplicities are required to achieve better error-correcting performance. Moreover, for general ASD algorithms, the points in the same code position may have different multiplicities. In this paper, a generalized backward interpolation algorithm is proposed through constructing equivalent Grobner basis. It is capable of reducing the multiplicity of each point in the same code position by one at a time until zero, and the multiplicity of each point can be different. As an example, the proposed scheme is applied to a Chase-type decoding that has multiplicity two in the flipping points, and efficient hardware architectures are developed. For a (255, 239) RS code with eight test vectors, employing the proposed backward interpolation leads to 18% area reduction and 23% speedup compared to repeating the interpolation over the flipping points for each test vector. [ABSTRACT FROM PUBLISHER]

This paper proposes a data bandwidth-oriented motion estimation design for resource-limited mobile video applications using an integrated bandwidth rate distortion optimization framework. This framework predicts and allocates the appropriate data bandwidth for motion estimation under a limited bandwidth supply to fit a dynamically changing bandwidth supply. The simulation results show that our proposed algorithm can achieve 66% and 41% memory bandwidth savings while maintaining an equivalent rate-distortion performance and meeting real-time targets, when compared with conventional approaches for low-motion and high-motion D1 (704\,\times\,576)-size video, respectively. The final implementation costs 122 K gate counts with TSMC 0.13-\mum CMOS technology and consumes 74 mW of power for D1 resolution at 30 frames/s which is 40% of that achieved in previous designs. [ABSTRACT FROM AUTHOR]

In this paper, a pipelined architecture using CORDIC for realization of transform domain equalizer is presented. Transform domain equalizer has much faster convergence than its time domain counterpart for practical hardware realization having nonzero adaptation delay. Here running DFT is employed as the transform, and CORDIC is used for realization of running DFT. Pipelining is applied throughout the architecture, thus limiting the critical path delay to the propagation delay of a single 16 bit adder for 16 bit arithmetic. For N tap equalizer, primary clock speed is N times of the sample clock speed, so that on arrival of each sample, the computation of whole transform and weight update is possible. In the proposed architecture, hardware complexity is reduced by fully utilizing the pipeline without using parallel structures. The adaptation delay is only 2 sample clock periods resulting in fast convergence. The proposed architecture is suitable for VLSI implementation with primary clock speed limited by the binary adder propagation delay which could be as low as 2 ns in the present state-of-the-art technology. [ABSTRACT FROM AUTHOR]

A new decoder architecture for nonbinary low-density parity-check (LDPC) codes is presented in this paper to reduce the hardware operational complexity in VLSI implementations. The low decoding complexity is achieved by employing adaptive message control (AMC) that dynamically trims the message length of belief information to reduce the amount of memory accesses and arithmetic operations. To implement the proposed AMC, we develop the architecture of a horizontal sequential nonbinary LDPC decoder. Key components in the architecture have been designed with the consideration of variable message lengths to leverage the benefit of the proposed AMC. Simulation results demonstrate that the proposed nonbinary LDPC decoder architecture can significantly reduce hardware operations and power consumption as compared with existing work with negligible performance degradation. [ABSTRACT FROM AUTHOR]

A discrete time continuous level VLSI architecture in current mode is proposed to implement 1-D Discrete Haar Wavelet Transform (DHWT). This architecture is implemented in current mode on unquantized samples, to achieve high dynamic range that is suitable for high frequency applications. DHWT is performed on the incoming samples which are available continuously from a real-time system. In this implementation, data converters are not needed, that leads to a reduction in complexity and savings in area. [ABSTRACT FROM AUTHOR]

A pipelined architecture is developed for a Sequential Monte Carlo (SMC) receiver that performs joint channel estimation and data detection. The promising feature of the proposed SMC receiver is achieving the near-bound performance in fading channels without using any decision feedback, training or pilot symbols. The proposed architecture exploits the parallelism intrinsic to the algorithm and consists of three blocks, i.e., the SMC core, weight calculator, and resampler. Hardware efficient/parallel architectures for each functional block including the resampling block is developed. The novel feature of the proposed architecture is that makes the execution time of the resampling independent of the distributions of the weights. Despite the alternatives in the literature, the proposed scheme achieves a very small execution time by pipelining the resampling and sampling steps. Moreover, it is scalable for high levels of parallelism, has lower memory usage, fixed routing time, and has close to the ideal performance. Finally, an ASIC implementation of the resampling core is presented in a 0.13 μm CMOS technology, which operates at 200 MHz with 0.8 mm of silicon area. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel path-preserving trellis-search (PPTS) algorithm and its high-speed VLSI architecture for soft-output multiple-input-multiple-output (MIMO) detection. We represent the search space of the MIMO signal with an unconstrained trellis, where each node in stage k of the trellis maps to a possible complex-valued symbol transmitted by antenna k. Based on the trellis model, we convert the soft-output MIMO detection problem into a multiple shortest paths problem subject to the constraint that every trellis node must be covered in this set of paths. The PPTS detector is guaranteed to have soft information for every possible symbol transmitted on every antenna so that the log-likelihood ratio (LLR) for each transmitted data bit can be more accurately formed. Simulation results show that the PPTS algorithm can achieve near-optimal error performance with a low search complexity. The PPTS algorithm is a hardware-friendly data-parallel algorithm because the search operations are evenly distributed among multiple trellis nodes for parallel processing. As a case study, we have designed and synthesized a fully-parallel systolic-array detector and two folded detectors for a 4 \times 4 16-QAM system using a 1.08 V TSMC 65-nm CMOS technology. With a 1.18 mm^2 core area, the folded detector can achieve a throughput of 2.1 Gbps. With a 3.19 mm^2 core area, the fully-parallel systolic-array detector can achieve a throughput of 6.4 Gbps. [ABSTRACT FROM AUTHOR]

Generalized minimum distance (GMD) decoding of Reed-Solomon (RS) codes can correct more errors than conventional hard-decision decoding by running error-and-erasure decoding multiple times for different erasure patterns. The latency of the GMD decoding can be reduced by the Kötter's one-pass decoding scheme. This scheme first carries out an error-only hard-decision decoding. Then all pairs of error-erasure locators and evaluators are derived iteratively in one run based on the result of the error-only decoding. In this paper, a more efficient interpolation-based one-pass GMD decoding scheme is studied. Applying the re-encoding and coordinate transformation, the result of erasure-only decoding can be directly derived. Then the locator and evaluator pairs for other erasure patterns are generated iteratively by applying interpolation. A simplified polynomial selection scheme is proposed to pass only one pair of locator and evaluator to successive decoding steps and a low-complexity parallel Chien search architecture is developed to implement this selection scheme. With the proposed polynomial selection architecture, the interpolation can run at the full speed to greatly increase the throughput. After efficient architectures and effective optimizations are employed, a generalized hardware complexity analysis is provided for the proposed interpolation-based decoder. For a (255, 239) RS code, the high-speed interpolation-based one-pass GMD decoder can achieve 53% higher throughput than the Kötter's decoder with slightly more hardware requirement. In terms of speed-over-area ratio, our design is 51% more efficient. In addition, compared to other soft-decision decoders, the high-speed interpolation-based GMD decoder can achieve better performance-complexity tradeoff. [ABSTRACT FROM AUTHOR]

Abstract: The embedded block coding with optimized truncation (EBCOT) algorithm is the heart of the JPEG 2000 image compression system. The MQ coder used in this algorithm restricts throughput of the EBCOT because there is very high correlation among all procedures to be performed in it. To overcome this obstacle, a high throughput MQ coder architecture is presented in this paper. To accomplish this, we have studied the number of rotations performed and the rate of byte emission in an image. This study reveals that in an image, on an average 75.03% and 22.72% of time one and two shifts occur, respectively. Similarly, about 5.5% of time two bytes are emitted concurrently. Based on these facts, a new MQ coder architecture is proposed which is capable of consuming one symbol per clock cycle. The throughput of this coder is improved by operating the renormalization and byte out stages concurrently. To reduce the hardware cost, synchronous shifters are used instead of hard shifters. The proposed architecture is implemented on Stratix FPGA and is capable of operating at 145.9MHz. Memory requirement of the proposed architecture is reduced by a minimum of 66% compared to those of the other existing architectures. Relative figure of merit is computed to compare the overall efficiency of all architectures which show that the proposed architecture provides good balance between the throughput and hardware cost. [Copyright &y& Elsevier]

In this paper, we present a new hardware-oriented, modified diamond search (HMDS) algorithm, for fast integer pel, motion estimation in H.264/AVC. We also present our co-designed, low power very large scale integration (VLSI) architecture for HMDS. The goal of HMDS is to enable the support of high quality video on low power mobile devices and low bit rate applications which typically use H.264/AVC baseline profile at levels 1–2. Our experiments use standard test sequences ranging from QCIF to high-definition 1280\,\times\,720 p video. The proposed VLSI architecture is prototyped as an field-programable gate array (FPGA)-based field programable system-on-chip. Our results show that HMDS on average has better rate-distortion performance and speedup, compared to previous state-of-the-art fast motion estimation algorithms, while its losses compared to full search motion estimation, are insignificant. Our prototyped architecture is more hardware-efficient than previous FPGA-based architectures in terms of power consumption, area, throughput, and memory utilization. We also show that its performance in terms of maximum frequency, minimum frequency, transistor count, and power consumption are comparable to that of state-of-the-art architectures implemented on application-specific integrated circuits. [ABSTRACT FROM AUTHOR]

Abstract: Motion estimation (ME) is the most critical component of a video coding standard. H.264/AVC adopts the variable block size motion estimation (VBSME) to obtain excellent coding efficiency, but the high computational complexity makes design difficult. This paper presents an effective processor chip for integer motion estimation (IME) in H264/AVC based on the full-search block-matching algorithm (FSBMA). It uses architecture with a configurable 2D systolic array to obtain a high data reuse of search area. This systolic array supports a three-direction scan format in which only one row of pixels is changed between the two adjacent subblocks, thus reducing the memory accesses and saving clock cycles. A computing array of 64 PEs calculates the SAD of basic 4×4 subblocks and a modified Lagrangian cost is used as matching criterion to find the best 41 variable-size blocks by means of a tree pipeline parallel architecture. Finally, a mode decision module uses serial data flow to find the best mode by comparing the total minimum Lagrangian costs. The IME processor chip was designed in UMC 0.18μm technology resulting in a circuit with only 32.3k gates and 6 RAMs (total 59kBits on-chip memory). In typical working conditions (25°C, 1.8V), a clock frequency of 300MHz can be estimated with a processing capacity for HDTV (1920×1088 @ 30fps) and a search range of 32×32. [Copyright &y& Elsevier]

This paper studies finite word-length effects on two different VLSI architectures of integer discrete wavelet transforms (DWT). The two DWT architectures representing two extreme cases are Scheme 1: basis correlation, and Scheme 2: pyramidal algorithm. For signal-to-noise ratio (SNR) evaluations, we consider various values of the length of integer word (W). Our experiments show that W is critical for both schemes, although both schemes perform almost equivalently. We also show that Scheme 1 and Scheme 2 have computational complexities O(N²) and O(N), respectively. The paper concludes that the word length W has similar critical impacts on the quality of integer DWT of both Schemes, hence Scheme 2 should be used based on lower computational complexity reason. [ABSTRACT FROM AUTHOR]

H.264/AVC intra-frame encoding contains several computation-intensive coding tools that form a long data dependency loop that is difficult to speed up. In this paper, we present a low-power and high-performance H.264/AVC intra-frame encoder. We propose several novel approaches to alleviate the performance bottleneck caused by the long data dependency loop among 4\,\times\,4 luma blocks, integrate an efficient CABAC entropy encoder, and apply a clock-gating technique to reduce power consumption. Synthesized into a TSMC 0.13 \mum CMOS cell library, our design requires 265.3 K gates at 114 MHz and consumes 23.56 mW to encode 1080pHD (1920\,\times\,1088) video sequences at 30 frames per second (fps). It also delivers the same video quality as the H.264/AVC reference software. Compared with all state-of-the-art designs, our design has a lower working frequency and achieves both better bit-rate saving and lower power consumption. [ABSTRACT FROM AUTHOR]

Abstract: This paper presents a practically realisable VLSI architecture for a 4×4 16-QAM MIMO wireless communication system using the Vertical Bell Labs Layered Space-Time (V-BLAST) detection scheme. The proposed implementation employs the QR-factorisation technique. The design and optimisation of the pre-decoder block are carried out using the COordinate Rotation DIgital Computer (CORDIC) processors. In order to avoid the numerical problems associated with Back Substitution (BS) based Symbol Interference Cancellation (SIC), a modified BS-SIC architecture that eliminates the need for division and multiplication is proposed. Not only does this substantially reduce the hardware cost, but also enjoys improved numerical stability. As the decoder hardware design can also be simplified by rendering it oblivious to the power normalisation in the transmitter side of the MIMO wireless system, we have designed a matching compensation unit at the receiver. The resulting VLSI architecture was implemented on an Altera Stratix Field Programmable Gate Array (FPGA) platform and on a 0.18μm Application Specific Integrated Circuits (ASIC) platform. Detection throughput ratings of 149Mbps and 212Mbps were achieved. However, the lower hardware complexity of the BS-SIC based decoder architecture comes at the cost of a degradation in the Bit Error Rate (BER) performance with respect to the original higher complexity V-BLAST. Therefore, we also propose a novel parallel decoding scheme that is aimed at improving the system BER. This novel scheme allows for a compromise between the hardware overhead and the BER performance. As the hardware complexity is increased, the performance approaches the original V-BLAST limit. [Copyright &y& Elsevier]

The present article proposes a high-performance architecture for the Two-Step Search algorithm, which is used in half-pixel motion estimation. As motion estimation calls for intense computation on a large number of pixels stored in memory, frequent memory access is involved in this operation. In the present article, an architecture, which is based on an intelligent memory configuration to contain the required large memory bandwidth, has been proposed for implementing the Two-Step Search algorithm for variable block sizes as recommended by H.264 standard. The present architecture has been compared with a reported architecture. It has been found that the proposed architecture can process up to 33% more number of High Definition Tele-Vision frames (of size 1280×720) and also consumes 5% less power by sacrificing only about 1.6% of the total chip area. [ABSTRACT FROM AUTHOR]

Image pipeline processing is crucial to generating high quality images in applications using complementary metal-oxide-semiconductor (CMOS)/charge-coupled device sensors. The on-chip line buffer normally dominates the total area and power dissipation due to the needed filter window buffering. As image resolution and filter support increase, the area and power requirement increase accordingly. This paper presents a novel pyramid architecture to efficiently process a system that the image pipeline is between an image sensor and video coding engine. By utilizing the features of the pyramid structure and block-based video/image encoders, the proposed architecture is scalable from low to high image resolution and filter size. The input image is first partitioned into floors of tiles to reduce the frame line buffer. Two computing schemes, immediate result reuse and vertical snack scan, are utilized to reduce the overlapping redundant computations. A 90 nm CMOS chip design with 7\,\times\,5 filter support for 3840\,\times\,2160 quad full high definition video at 30 frames/s is designed to demonstrate the performance of power and area efficiency. Compared with traditional architectures with frame line buffers, the proposed design has shown that the power consumption is reduced by 25% to 108 mW from 145 mW. The chip area is reduced by 65% to 309 K from 888 K logic gates. The external memory bandwidth increases to 8286 Mbit/s from 5972 Mbit/s for YUV4:2:0, from 7963 Mbit/s for YUV4:2:2, and is reduced by 30% from 11944 Mbit/s for YUV4:4:4. [ABSTRACT FROM PUBLISHER]

A multirate receiver for WCDMA systems based on the adaptive signature method was designed and implemented. We employed an adaptive signature algorithm to consider two well-known multirate schemes, namely, the low rate and the high rate detector for variable spreading factor systems. In monorate scenarios, numerical experimentations showed that the adaptive signature method outperforms the Rake receiver and reaches the performances of the soft 4-stage multistage parallel interference cancellation receiver. In multirate scenarios, the performance comparison of two multirate schemes in floating-point and fixed-point was analyzed. Reusing the existing hardware architecture previously developed for monorate systems, we targeted the hardware implementation of these two multirate schemes on FPGA components. [ABSTRACT FROM AUTHOR]

Novel decomposed lifting scheme (DLS) is presented to perform one-dimensional (1D) discrete wavelet transform (DWT) with consistent data flow in both row and column dimension. Based on the proposed DLS, intermediate data can be transferred seamlessly between the column processor and the row processor in the hardware implementation of two-dimensional (2D) DWT, resulting in the reduction of on-chip memory, output latency and control complexity. Moreover, the implementation of 2D DWT can be easily extended to achieve higher processing speed with controlled increase of hardware cost. Memory-efficient and high-speed architectures are proposed to implement 2D DWT for JPEG2000, which are called fast architecture (FA) and high-speed architecture (HA). FA and HA can perform 2D DWT in N 2/ 2 and N 2/ 4 clock cycles for an N× N image, respectively, but the required internal memory is only 4N for 9/7 DWT and 2N for 5/3 DWT. Compared with the works reported in previous literature, the proposed designs provide excellent performance in hardware cost, control complexity, output latency and computing time. The proposed designs were implemented to process 2D 9/7 DWT in SMIC 0.18 μm CMOS logic fabrication with 4 KB internal memory for the image size 512 × 512. The areas are only 999137 um 2 and 1333054 um 2 for FA and HA, respectively, but the operation frequency can be up to 150 MHz. [ABSTRACT FROM AUTHOR]

Abstract: There are abundant intra and inter prediction modes in the AVS video coding standard. Rate distortion optimized mode decision can fully utilize this flexibility to improve the spatio-temporal prediction efficiency and maximize the coding efficiency. However, the implementation complexity is dramatically high due to huge throughput burden. Hardware oriented mode decision algorithm is tailored for VLSI implementation in this work for high definition video coding. Mode preselection is employed to alleviate the dramatic throughout burden. Also, intelligent pipeline scheduling mechanism is proposed to break the intrinsic data dependency in intra prediction, which is directly related with mode decision. The proposed simplified algorithm is well-suited for hardware implementation with small performance penalty. Finally, the VLSI architecture is proposed with good trade off between circuit consumption and rate distortion performance. [ABSTRACT FROM AUTHOR]

This brief presents an innovative high-speed context-adaptive variable-length encoder. First, a direct forward algorithm rather than backward tracking is proposed to compute the coding parameters. The forward computation without data reordering can shorten the latency time and the processing cycle. Based on the algorithm, the real-time chip is designed with a parallel structure and pipelined control, which can encode one codeword per cycle. The maximum processing time for one block is the number of nonzero coefficients (NC)+4 cycles. The output bit rate can achieve 125M/s when implemented with 0.18-µm CMOS technology. The chip occupies about 15k gates, and the power dissipation is about 5.38 mW. [ABSTRACT FROM AUTHOR]

Variable block size motion estimation (VBSME) is one of several contributors to H.264/AVC's excellent coding efficiency. However, its high computational complexity and huge memory traffic make deign difficult. In this paper, we propose a memory-efficient and highly parallel VLSI architecture for full search VBSME (FSVBSME). Our architecture consists of 16 2-D arrays each consists of 16 x 16 processing elements (PEs). Four arrays form a group to match in parallel four reference blocks against one current block. Four groups perform block matching for four current blocks in a pipelined fashion. Taking advantage of overlapping among multiple reference blocks of a current block and between search windows of adjacent current blocks, we propose a novel data reuse scheme to reduce memory access. Compared with the popular Level C data reuse scheme, our approach can save 98% of on-chip memory access with only 25% of local memory overhead. Synthesized into a TSMC 180-nm CMOS cell library, our design is capable of processing 1920 x 1088 30 fps video when running at 130 MHz. The architecture is scalable for wider search range, multiple reference frames and pixel truncation as well as down sampling. We suggest a criterion called design efficiency for comparing different works. It shows that the proposed design is 72% more efficient than the best design to date. [ABSTRACT FROM AUTHOR]

Variable-block-size motion estimation (VBSME) is one of the contributors to H.264/Advanced Video Coding (AVC)'s excellent coding efficiency. Due to its high computational complexity, however, VBSME needs acceleration for real-time high-resolution applications. We propose a high-performance hardware architecture for H.264/AVC fractional motion estimation. Our architecture consists of three parallel processing engines, one for 4 x4 and 8 x 8 blocks, one for 8 x 4 and 4 x 8 blocks, and another for the remaining type of blocks. In addition, we propose a resource-sharing scheme which saves 33% of hardware cost for the computation of the sum of absolute transformed difference. Synthesized into a Taiwan Semiconductor Manufacturing Company (TSMC) 180-nm CMOS cell library, our 321-K gate design only needs to run at 154 MHz when encoding a 1920 x 1088 video at 30 frames per second. Compared with a most comparable previous work that consumes 311 K gates and runs at 200 MHz, our proposed architecture is more efficient. [ABSTRACT FROM AUTHOR]

This paper presents an architecture of the lifting based running 3-D discrete wavelet transform (DWT), which is a powerful image and video compression algorithm. The proposed design is one of the first lifting based complete 3-DDWT architectures without group of pictures restriction. The new computing technique based on analysis of lifting signal flow graph minimizes the storage requirement. This architecture enjoys reduced memory referencing and related low power consumption, low latency, and high throughput compared to those of earlier reported works. The proposed architecture has been successfully implemented on Xilinx Virtex-IV series field-programmable gate array, offering a speed of 321 MHz, making it suitable for realtime compression even with large frame dimensions. Moreover, the architecture is fully scalable beyond the present coherent Daubechies filterbank (9, 7). [ABSTRACT FROM AUTHOR]

Recently developed algebraic soft-decision (ASD) decoding of Reed-Solomon (RS) codes have attracted much interest due to the fact that they can achieve significant coding gain with polynomial complexity. One major step of ASD decoding is the interpolation. Available interpolation algorithms can only add interpolation points or increase interpolation multiplicities. However, backward interpolation, which eliminates interpolation points or reduces interpolation multiplicities, is indispensable to enable the reusing of interpolation results in the following two scenarios: 1) interpolation needs to be carried out on multiple test vectors, which share common entries and 2) iterative ASD decoding where interpolation points have decreasing multiplicities. Examples for these cases are the low-complexity Chase (LCC) decoding and bit-level generalized minimum distance (BGMD) decoding. With lower complexity, these algorithms can achieve similar or higher coding gain than other practical ASD algorithms. In this paper, we propose novel backward interpolation schemes and corresponding efficient implementation architectures for LCC and BGMD decoding through constructing equivalent Gröbner bases. The proposed architectures share computational units with forward interpolation architectures. Hence, the area overhead for incorporating the backward interpolation is very small. Substantial area saving or speedup can be achieved by using the backward interpolation. When the proposed architecture is applied to the LCC decoding of a (255, 239) RS code with η = 3, the area is reduced to 39% of those required by prior architectures. In terms of speed/area ratio, the proposed architecture is 48% more efficient than the best available architecture. For the BGMD decoding of the same code, the proposed architecture can achieve around 20% higher efficiency. [ABSTRACT FROM AUTHOR]

This paper presents a method to reduce the computation and memory access for variable block size motion estimation (ME) using pixel truncation. Previous work has focused on implementing pixel truncation using a fixed-block- size (16 x 16 pixels) ME. However, pixel truncation fails to give satisfactory results for smaller block partitions. In this paper, we analyze the effect of truncating pixels for smaller block partitions and propose a method to improve the frame prediction. Our method is able to reduce the total computation and memory access compared to conventional full-search method without significantly degrading picture quality. With unique data arrangement, the proposed architectures are able to save up to 53% energy compared to the conventional full-search architecture. This makes such architectures attractive for H.264 application in future mobile devices. [ABSTRACT FROM AUTHOR]

A VLSI encoder and decoder implementation for the IEEE 802.16 WiMax convolutional turbo code is presented. Architectural choices employed to achieve high throughput, while granting a limited occupation of resources, are addressed both for the encoder and decoder side, including also the subblock interleaving and symbol selection functions specified in the standard. The complete encoder and decoder architectures, implemented on a 0.13 μm standard cell technology, sustain a decoded throughput of more than 90 Mb/s with a 200 MHz clock frequency. The encoder has the complexity of 9.2 kgate of logic and 187.2 kbit of memory, whereas the complete decoder requires 167.7 kgate and 1163 kbit. [ABSTRACT FROM AUTHOR]

Variable block-size motion estimation (VBSME) has become an important technique in H.264/A VC to improve video quality. In this paper, we propose a scalable VLSI architecture for VBSME in H.264/A VC based on a full-search motion estimation algorithm. A new scan order is introduced to re-use the sum of absolute differences (SAD) values of smaller sub-blocks on an "as-early-as-possible" basis, thus the complexity of the required hardware resources, such as registers, multiplexers, and controls is reduced. It also spreads the timing for the final SAD outputs so that the number of output buses is reduced. The architecture is flexible and scalable with regard to the size of the searching windows and PE arrays. Compared to the conventional approaches, the architecture shows higher throughput rate with less hardware. After logic synthesis using DongbuAnam 0.18 μm standard cell library, the number of gates is 39K (16 PEs) in two-input equivalent NAND gates and the maximum operating clock frequency is 416 MHz (256 fps@CIF). [ABSTRACT FROM AUTHOR]

This paper presents an HDTV video decoder core that is able to decode MPEG-2, MPEG-4 A VC and VC-I formats and is fully compatible with the Blu-ray Disc standard. The core has two major features which achieve low-cost hardware implementation for three different standards. First, a novel re-configurable architecture is adopted to realize reduced hardware for three different variable length coding tables. A hybrid architecture that consists of a cell array and coefficients memory is introduced By considering the trade-off between performance and cost, the cell array can compare a variable number of bits in a flexible manner. Second, a data compression method suitable for all video decoding standards is applied to reduce memory data usage and access bandwidth. A compression syntax based on Run-Level encoding with Exp-Golomb tables is used to achieve both low compression workload and reasonable memory cost. The core is implemented by top-down HDL basis approach, and the circuit volume is 1.5Mgates with 9Onm CMOS technology and operation clock.frequency is 162MHz for 1080i at 30fr/s. [ABSTRACT FROM AUTHOR]

This paper presents a high-throughput decoder architecture for generic quasi-cyclic low-density parity-check (QC-LDPC) codes. Various optimizations are employed to increase the clock speed. A row permutation scheme is proposed to significantly simplify the implementation of the shuffle network in LDPC decoder. An approximate layered decoding approach is explored to reduce the critical path of the layered LDPC decoder. The computation core is further optimized to reduce the computation delay. It is estimated that 4.7 Gb/s decoding throughput can be achieved at 15 iterations using the current technology. [ABSTRACT FROM AUTHOR]

This paper presents a HD1080p 30-frames/s H.264 intra encoder operated at 140 MHz with just 94 K gate count and 0.72-mm 2 core area for digital video recorder or digital still camera applications. To achieve high throughput and low area cost for high-definition video, we apply the modified three-step fast intra prediction technique to reduce the cycle count while keeping the quality as close as full search. Then, in architecture scheduling, we further adopt the variable pixel parallelism instead of constant four-pixel parallelism to speed up performance on the critical intra prediction part while keeping other parts unchanged for low area cost. The achieved design only needs half of the working frequency and reduces the gate count cost by 23.5% compared with the previous design with the same HD720p 30-frames/s requirement. Besides, our design at 140 MHz can support HD1080p 30 frames/s for digital video encoder or 4096 × 2304 images with 6.78 frames/s for digital still camera application. [ABSTRACT FROM AUTHOR]

Wide-angle cameras are widely used in surveillance and medical imaging applications nowadays. Images captured by wide-angle lens suffer from barrel distortion which means that the outer regions of the image are compressed more than the inner one. A low-cost high-speed VLSI implementation for barrel distortion correction is presented in this brief. In our simulation, the pro- posed circuit can achieve 200 MHz with 45 K gate counts by using TSMC 0.18 μm technology. Compared with the previous distortion correction design, our circuit requires less hardware cost and achieves faster working speed. [ABSTRACT FROM AUTHOR]

In this paper, we propose an effective VLSI architecture of sub-pixel interpolation for motion compensation in the AVS HDTV decoder. To utilize the similar arithmetical operations of 15 luma sub-pixel positions, three types of interpolation filters are proposed. A simplified multiplier is presented due to the limited range of input in the chroma interpolation process. To improve the processing throughput, a parallel and pipelined computing architecture is adopted. The simulation results show that the proposed hardware implementation can satisfy the real-time constraint for the AVS HDTV (1 920×1 088) 30 fps decoder by operating at 108 MHz with 38.18k logic gates. Meanwhile, it costs only 216 cycles to accomplish one macroblock, which means the B frame sub-pixel interpolation can be realized by using only one set of the proposed architecture under real-time constraints. [ABSTRACT FROM AUTHOR]

This paper presents an efficient architecture of an application specific processor (ASP) designed for the deblocking filter algorithm of the H.264 video compression standard. Several optimization techniques at different design levels, such as vector register, pipeline processing, very long instruction word (VLIW) processor, and predication, are utilized in this design. The proposed ASP can meet the real timeconstraint of the deblocking filter algorithm for the 16:9 video format (4690 x 2304) at 30 frames per second (fps) at 200-MHz clock rate. [ABSTRACT FROM AUTHOR]

Modular exponentiation with a large modulus, which is usually accomplished by repeated modular multiplications, has been widely used in public key cryptosystems for secured data communications. To speed up the computation, the Montgomery modular multiplication algorithm is used to relax the process of quotient determination, and the carry-save addition (CSA) is employed to reduce the critical path delay. In this paper, based on the inherent data dependency between the modular multiplication and square operations in the H-algorithm of modular exponentiation, we present a new modular exponentiation architecture with a unified modular multiplication/square module and show how to reduce the number of input operands for the CSA tree by mathematical manipulation. The developed architecture has the following advantages. 1) There is no need to convert the carry-save form of an operand into its binary representation at the end of each modular multiplication. In this way, except the final step to get the result of modular exponentiation, the time-consuming carry propagation can then be eliminated. 2) The number of input operands for the CSA tree is reduced in a very efficient way. 3) The hardware saving is achieved with very limited impact on the original critical path delay when designed with two distinct modular multiplication and square components. Experimental results show that our modular exponentiation design obtains the least hardware complexity compared with the existing work and outperforms them in terms of area-time (AT) complexity as well. [ABSTRACT FROM AUTHOR]

To satisfy the high quality image compression requirement, the new JPEG XR compression standard is introduced. The analysis and architecture design with VLSI architecture of JPEG XR encoder are proposed in this paper which can encode 4.4:4 1920 × 1080 high definition photo in smooth. According to the simulation results, the throughput of the proposed design can encode 44.2 M samples/sec. This design can be used for digital photography applications to achieve low computation, low storage, and high dynamical range features. [ABSTRACT FROM AUTHOR]