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A group of new memory circuit techniques with the emerging FinFET technology are evaluated in this paper. Three independent-gate FinFET SRAM cells and two multi-threshold-voltage (multi-Vt) work-function engineered SRAM cells are compared for data stability, leakage power consumption, and cell area. The highest read stability is provided by the technique based on dynamically tuning the threshold voltages of the data access transistors during the read and write operations with independent-gate-bias. The read stability is enhanced by up to 92% with the minimum sized dynamic independent-gate-bias FinFET SRAM cells as compared to the minimum sized low-threshold-voltage tied-gate FinFET SRAM cells in a 32 nm FinFET technology. Alternatively, the lowest leakage power consumption and the smallest cell area are provided with the work-function engineered multi-Vt FinFET memory cells. The idle mode leakage power and the cell area are reduced by up to 65X and 25.5%, respectively, with the work-function engineered multi-Vt FinFET SRAM cells as compared to a standard low-threshold-voltage (low-Vt) tied-gate FinFET SRAM cell sized for comparable read stability.

Data stability of static random access memory (SRAM) circuits has become an important issue with the scaling of CMOS technology. Memory arrays are also important sources of leakage since the majority of transistors are utilized for on-chip memory in today's high performance microprocessors and systems-on-chips. The use of work-function engineering to control the threshold voltage of FinFETs is explored in this paper for achieving minimum sized multi-threshold-voltage (multi-Vt) six transistor (6T) SRAM cells with sufficient data stability and lower leakage power consumption characteristics. A work-function optimization methodology for designing low power and high speed memory circuits is presented. With the proposed multi-Vt design methodology based on gate work-function engineering, the leakage power is reduced by up to 65X as compared to a standard single low threshold voltage (single- low-Vt) SRAM circuit sized for similar data stability in a 32 nm FinFET technology.

A new seven transistors (7T) dual threshold voltage SRAM cell is proposed in this paper for simultaneously reducing the active and standby mode power consumption while enhancing the data stability and the read speed. With the new 7T SRAM cell, the storage nodes are isolated from the bitlines during a read operation, thereby enhancing the data stability as compared to the standard six transistors (6T) SRAM circuits. The transistors of the cross-coupled inverters are not on the critical read delay path with the new technique. Minimum sized dual-threshold-voltage transistors are therefore conveniently used in the cross-coupled inverters for significantly reducing the leakage power consumption without causing a degradation in the read speed. With the proposed 7T SRAM circuit, the static noise margin and the read speed are enhanced by up to 87% and 17%, respectively, as compared to the conventional 6T SRAM circuits. Furthermore, the leakage and the write power consumptions of the proposed dual-V, SRAM circuit are reduced by up to 66% and 35%, respectively, as compared to the conventional 6T SRAM circuits in a 65 nm CMOS technology.

A new SRAM circuit technique based on dynamically adjusting the wordline voltage swing is proposed in this paper for reducing the leakage power consumption and enhancing the data stability in static memory banks. With the proposed technique, the wordline voltage swing is reduced in order to suppress the voltage disturbance at the data storage nodes during a read operation. The stability of a minimum sized standard six transistors (6T) SRAM cell is thereby significantly enhanced. Alternatively, during a write operation the wordline signal has a full voltage swing in order to achieve write-ability with a high write margin. With the proposed circuit technique, the static noise margin is enhanced by up to 122% as compared to the conventional full-voltage-swing 6T SRAM circuits with minimum sized transistors. Furthermore, the leakage power consumption with the proposed technique is reduced by 51% as compared to the conventional full-voltage-swing circuits sized for data stability in a 65nm CMOS technology.

Brute-force sequential circuits with reduced clock load and simpler circuitry are widely used in the state-of-the-art integrated circuits. In this paper, new brute-force independent-gate FinFET sequential circuits are evaluated for power consumption, speed, and noise immunity characteristics at different process corners under parameter fluctuations in a 32 nm FinFET technology. With the independent-gate FinFET latches and flip-flops, the total active mode power consumption, the clock power, and the average leakage power are reduced by up to 47%, 32%, and 37%, respectively, while maintaining similar speed and data stability as compared to the circuits with tied-gate FinFETs across different process corners. Furthermore, the area is reduced by 20% with the new sequential circuits due to the smaller transistors as compared to the circuits with tied-gate FinFETs.

A new six transistor (6 T) SRAM cell with PMOS access transistors is proposed in this paper for reducing the leakage power consumption while enhancing the data stability and the integration density of FinFET memory circuits. With the proposed SRAM circuit, the voltage disturbance at the data storage nodes during a read operation is reduced by utilizing PMOS access transistors. The read stability is enhanced by 60% while reducing the leakage power by 21% as compared to a standard tied-gate FinFET SRAM cell with the same size transistors. One gate of each pull-up FinFET of the cross- coupled inverters is permanently disabled in order to achieve write-ability with minimum sized transistors. The proposed independent-gate FinFET SRAM circuit with P-type data access transistors reduces the idle mode leakage power, the read power, the write power, and the cell area by 61%, 20%, 11.4%, and 17.5%, respectively, as compared to a standard tied-gate FinFET SRAM cell sized for similar data stability in a 32 nm FinFET technology.

The previous MTCMOS sequential circuit techniques with data preserving sleep modes require either a distributed sleep switch circuit structure with a significant area overhead or a complex peripheral control circuitry for preserving and restoring the data. Two new master-slave MTCMOS flip-flops with centralized sleep switches providing a low leakage and low overhead sleep mode with data retention capability are presented in this paper. A quasi-SRAM structure is combined with the slave latch of the proposed flip-flops. The already existing sleep signal of the MTCMOS circuitry is also used for controlling the data retention and restoration operations, thereby eliminating the need for any extra control signals with the new flip-flops. Furthermore, the leakage power consumption with the proposed techniques is reduced by up to 42.5% as compared to the previously published MTCMOS circuits.

Data stability of Static Random Access Memory (SRAM) circuits has become an important issue with the scaling of CMOS technology. Memory arrays are also an important source of leakage since the majority of transistors are utilized for on-chip caches in today's high performance microprocessors. A six transistor (6T) SRAM cell based on independent-gate FinFET technology (IG-FinFET) is described in this paper for simultaneously reducing the active and standby mode power consumption while enhancing the data stability and the integration density. With the independent-gate FinFET SRAM cell, the back gates of the access transistors are permanently disabled in order to enhance the data stability. The back gates of the pull-up FinFETs in the cross-coupled inverters are also permanently disabled to achieve write ability. Functionality and sufficient read stability are achieved with minimum sized transistors with the independent-gate-bias technique. The IG- FinFET SRAM cell reduces the idle mode leakage power, the active mode read power, the active mode write power, the write delay, and the cell area by up to 36%, 26%, 24%, 20%, and 12.4%, respectively, as compared to a standard tied-gate FinFET SRAM cell with similar read static-noise-margin in a 32 nm FinFET technology.

Data stability of static random access memory (SRAM) circuits has become an important issue with the scaling of CMOS technology. Memory arrays are also an important source of leakage since the majority of transistors are utilized for on-chip caches in today's high performance microprocessors. Two six transistor SRAM cells based on independent-gate FinFET technology (IG-FinFET) are described in this paper for simultaneously reducing the active and standby mode power consumption while enhancing the data stability and the integration density. With the first independent-gate FinFET SRAM cell, one gate of each double-gate access and pull-up transistor is permanently disabled in order to enhance the data stability while achieving write-ability with minimum sized transistors. With the second independent-gate FinFET SRAM cell, the threshold voltages of the access transistors are dynamically adjusted during circuit operation in order to maximize the memory integration density without sacrificing the performance and stability. The read stability is enhanced by up to 92% with the IG-FinFET SRAM cells as compared to a tied- gate FinFET SRAM cell with the same size transistors in a 32 nm FinFET technology. Furthermore, with the IG-FinFET SRAM cells, the idle mode leakage power and the cell area are reduced by up to 36% and 11%, respectively, as compared to a standard tied-gate FinFET SRAM cell sized for comparable read stability in a 32 nm FinFET technology.

Clock distribution network consumes a significant portion of the total chip power since the clock signal has the highest activity factor and drives the largest capacitive load in a synchronous integrated circuit. A new algorithm is proposed in this paper for buffer insertion and sizing in an H-tree clock distribution network. The objective of the algorithm is to minimize the total power consumption while satisfying the maximum acceptable clock transition time constraints at the leaves of the clock distribution network for maintaining high- performance. The algorithm employs non-uniform buffer insertion and progressive relaxation of the transition time requirements from the leaves to the root of the clock distribution network. The proposed algorithm provides up to 30% savings in the total power consumption as compared to a standard algorithm with uniform buffer insertion aimed at maintaining uniform transition time constraints at all the nodes of a clock tree.

Scaling of single-gate bulk MOSFET faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the subthreshold and gate-oxide leakage currents. Double-gate FinFET technology mitigates this limitation by the excellent control over a thin silicon body by two electrically coupled gates. In this paper a variable threshold voltage keeper circuit technique using independent-gate FinFET technology is proposed for simultaneous power reduction and speed enhancement in domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. With the variable threshold voltage keeper circuit technique the evaluation speed is enhanced by up to 55% while reducing power consumption by up to 57% as compared to a standard domino logic circuit designed for similar noise margin in a 32 nm FinFET technology.

A methodology based on supply voltage and frequency scaling for lowering the power consumption and temperature fluctuations induced skew of clock distribution networks is proposed in this paper. The clock signal is distributed globally at a scaled supply voltage and frequency. The optimum supply voltage that minimizes clock skew is 44% less than the nominal supply voltage in a 0.18μm CMOS technology. Combined frequency multiplier and level converter circuits are utilized at the leaves of the clock tree for restoring the standard full voltage swing clock signal with the higher target clock frequency in order to maintain the performance of the system. A novel dual-threshold-voltage frequency doubler with voltage level conversion capability, suppressed temperature fluctuations sensitivity, and low power consumption characteristics is presented. The temperature fluctuations induced skew and power consumption of the proposed dual-VDD/dual-frequency clock distribution network are reduced by up to 80% and 76%, respectively, as compared to a standard distribution network operating at the nominal supply voltage with the target system clock frequency.

Temperature dependent propagation delay characteristics of CMOS circuits will experience a complete reversal in the near future. Contrary to the older technology generations, the speed of standard zero-body-biased circuits in a 32 nm CMOS technology is enhanced when the temperature is increased at the nominal supply voltage. The enhancement of circuit speed provides new opportunities to lower the energy consumed by active circuits at elevated temperatures. Temperature-adaptive supply and threshold voltage tuning techniques are proposed in this paper to reduce the high temperature active mode energy consumption without degrading the circuit speed. Results indicate that the energy consumption can be lowered by up to 21% by dynamically scaling the supply voltage at elevated temperatures. An alternative technique based on temperature-adaptive reverse body-bias exponentially reduces the leakage currents as well as the parasitic junction capacitances of the MOSFETs. The temperature-adaptive threshold voltage tuning through reverse body-bias yields an active mode energy reduction by up to 29.8% as compared to the standard zero body-biased circuits at high temperatures.

Predictive technology model (PTM) enables early device and circuit characterization by providing the research community the expected profiles of devices in the future technologies. The parameters that need particularly accurate estimation are the speed and the power consumption. Fluctuations in the die temperature affect the device characteristics thereby altering the performance of integrated circuits. Furthermore, increase in the doping concentration and the enhanced electric fields in scaled devices tend to affect the rate of change of device parameter variations when the temperature fluctuates. For precise characterization of the MOSFETs at various temperatures, the parameters that model the temperature effects have to be accurately extracted. With the PTMs, however, the model parameters that characterize the temperature effects are typically transferred from an older technology generation without any change. This inappropriate transfer of parameters across different generations of predictive CMOS technologies may lead to gross errors during the characterization of CMOS circuits at various die temperatures. In this paper, the principle factors that determine the device characteristics when the temperature fluctuates are presented. The impact of technology scaling on the temperature fluctuation induced variation of the device parameters is illustrated. The parameters that model the temperature effects of the predictive technologies are compared. The study indicates that the device and circuit characterization with the PTMs may not be reliable at temperatures other than a single nominal temperature where the critical model parameters are extracted.

Employing multiple supply voltages (multi-VDD) is attractive for reducing the power consumption without sacrificing the speed of an integrated circuit (IC). In order to transfer signals among the circuits operating at different voltage levels specialized voltage interface circuits are required. Two novel multi-threshold voltage (multi-Vth) level converters are proposed in this paper. The proposed level converters are compared with the previously published circuits for different values of the lower supply voltage. When the circuits are individually optimized for minimum power consumption in a 0.18mum CMOS technology, the proposed level converters offer significant power savings of up to 70% as compared to the previously published circuits. Alternatively, when the circuits are individually optimized for minimum propagation delay, speed is enhanced by up to 78% with the proposed circuits.

Data in conventional six transistor (6T) static random access memory (SRAM) cells are vulnerable to noise due to the direct access to the data storage nodes through the bit lines during a read operation. A new nine transistor (9T) SRAM cell is proposed in this paper for simultaneously enhancing read stability and reducing leakage power consumption. The proposed 9T SRAM cell isolates the data from the bit lines during a read operation. The read static-noise-margin (SNM) of the proposed circuit is enhanced by 2times as compared to a standard 6T SRAM cell in a 65 nm CMOS technology. Furthermore, leakage power consumption of the new 9T SRAM cell is reduced by 22.9% as compared to the 6T SRAM cell. The read stability enhancement and leakage power reduction provided by the new circuit technique are also verified under process parameter variations.

A methodology based on supply voltage scaling for lowering the power consumption and temperature fluctuations induced skew of clock distribution networks is proposed in this paper. The clock signal is distributed globally at a lower optimum supply voltage. To maintain the speed of the system, a dual supply voltage (dual-VDD) clock distribution network is presented. Level converters are utilized to restore the standard full swing clock signal at the leaves of the low voltage clock distribution network. A novel level converter with low skew, propagation delay, and power consumption characteristics is presented. The optimum supply voltage that minimizes clock skew is 44% lower than the nominal supply voltage in a 0.18mum CMOS technology. The temperature fluctuations induced skew and power consumption of the proposed dualdual-VDD clock distribution network are 74% and 50.8% lower, respectively, as compared to a standard clock distribution network operating at the nominal supply voltage

Multi-threshold voltage CMOS (MTCMOS) has emerged as an increasingly popular technique for reducing the leakage energy consumption of idle circuits. The MTCMOS circuits, however, suffer from high energy overhead during the transitions between the active and standby modes. A new circuit technique is proposed in this paper to lower the energy overhead of these mode transitions for effective energy reduction with the MTCMOS circuits. The charge stored at the "virtual power" and "virtual ground" lines are recycled during the active-to-sleep-to-active mode transitions with the proposed technique. Applying the charge recycling MTCMOS circuit technique to a 32-bit Brent-Kung adder reduces the energy overhead due to the mode transitions by up to 36.3% as compared to the conventional MTCMOS circuits. Furthermore, the standby mode power consumption is reduced by up to 91.1% as compared to a standard Brent-Kung adder in a 65nm CMOS technology

Scaling of single-gate bulk MOSFET faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the leakage power. Double-gate MOSFET technologies mitigate this limitation by providing an excellent control over a thin silicon body with two electrically coupled gates. FinFET is the most attractive choice among the double-gate transistor architectures because of the self alignment of the two gates and the similarity of the fabrication steps to the existing standard CMOS technology. In this paper, new sequential circuits based on independent-gate FinFETs are proposed to simultaneously reduce the power consumption and the circuit area. With the proposed independently biased double-gate FinFET sequential circuits, the active power consumption, the leakage power, the clock power, and the circuit area are reduced by up to 46%, 42%, 26%, and 20%, respectively, as compared to the standard sequential circuits with tied-gate FinFETs.

A new circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power in domino logic circuits. PMOS-only sleep transistors are utilized along with a dual threshold voltage CMOS technology to place an idle domino circuit into a low leakage state. The effectiveness of the circuit technique is evaluated for a wide-temperature spectrum, considering both long and short idle periods. Assuming a short idle period at a temperature of 110/spl deg/C, up to 95.6% reduction in leakage power is observed as compared to standard dual threshold voltage domino circuits. Alternatively, assuming a long idle period at the room temperature, the circuit technique reduces the leakage power by up to 96.9% as compared to the standard dual threshold voltage domino logic circuits. Furthermore, by employing PMOS-only sleep transistors, the presented circuit technique reduces the total leakage power by up to 43.8% as compared to a previously published sleep scheme based on NMOS sleep transistors in a 45nm CMOS technology.

Temperature fluctuations alter threshold voltage, carrier mobility, and saturation velocity of a MOSFET. Temperature fluctuation induced variations in individual device parameters have unique effects on MOSFET drain current. Device parameters that characterize the variations in MOSFET current due to temperature fluctuations are identified in this paper for 180 nm and 65nm CMOS technologies. Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable circuit operation under temperature variations. A design methodology based on optimizing the supply voltage for temperature variation insensitive circuit performance is presented. Circuits display a temperature variation insensitive behavior when operated at a supply voltage 45% to 53% lower than the nominal supply voltage in a 180 nm CMOS technology. Similarly, the optimum supply voltages are 68% to 69% lower than the nominal supply voltage for circuits in a 65nm CMOS technology. The optimum supply voltages are similar for a diverse set of circuits in both technologies. The proposed technique of operating large scale designs at an optimum supply voltage for diminishing the performance sensitivity to temperature fluctuations is demonstrated to be feasible.

A design methodology based on optimizing the supply voltage for simultaneously achieving energy efficiency and temperature variation insensitive circuit performance is presented in this paper. Circuits exhibit temperature variation insensitive delay characteristics when operated at a supply voltage 67% to 68% lower than the nominal supply voltage. At scaled supply voltages, integrated circuits consume low power at the cost of reduced speed. The proposed design methodology of optimizing the supply voltage for temperature variation insensitive circuit performance is, therefore, particularly attractive for low power applications with relaxed speed requirements. The supply voltages that yield minimum energy and minimum energy-delay product are identified at two different temperatures for circuits in a 65 nm CMOS technology. The energy and speed at the supply voltages providing temperature variation insensitive propagation delay, minimum energy, and minimum energy-delay product are compared. Results indicate that energy efficient integrated circuits with deeply scaled supply voltages can also be made insensitive to temperature fluctuations by considering the temperature dependence of speed in the supply voltage optimization process.

A low overhead circuit technique is proposed in this paper for simultaneously reducing subthreshold and gate oxide leakage currents in domino logic circuits. PMOS sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. A sleep transistor added to the dynamic node strongly turns off all of the high threshold voltage transistors. Similarly, a sleep switch added to the output inverter exploits the initially high subthreshold and gate-oxide leakage currents for placing a circuit into an ultimately low leakage state. The proposed circuit technique lowers the total leakage power by 56.1% to 97.6% as compared to standard dual threshold voltage domino logic circuits. Similarly, a 4.6% to 50.6% reduction in total leakage power is observed as compared to a previously published sleep switch scheme in a 45nm CMOS technology.

A new low voltage swing circuit technique based on a dual threshold voltage CMOS technology is presented in this paper for simultaneously reducing active and standby mode power consumption and enhancing evaluation speed and noise immunity in domino logic circuits. The proposed circuit technique modifies both the upper and lower boundaries of the voltage swing at the dynamic node. Meanwhile, full voltage swing signals are maintained at inputs and outputs for robust and high speed operation. Power supply, ground, and threshold voltages are simultaneously optimized to minimize the power-delay product (PDP). The proposed technique reduces the PDP by up to 51.9% as compared to the standard full-swing circuits in a 45nm CMOS technology. The active mode power consumption is reduced by up to 40.4% due to the lower switching power required to charge/discharge the dynamic node. Furthermore, the evaluation speed and noise immunity are enhanced by up to 19.4% and 39.1%, respectively, as compared to the standard full-swing circuits. The proposed low swing technique also reduces the idle mode leakage power consumption of high fan-in domino gates by up to 84.2%.

The subthreshold and gate oxide leakage power characteristics of domino logic circuits are evaluated in this paper. The preferred input vectors and node voltage states are identified to minimize the total leakage power consumption in the sleep mode. New low leakage design guidelines based on the results are presented. Previous studies indicate that a discharged dynamic node voltage state with high inputs is preferable to reduce the subthreshold leakage power consumption in an idle dual threshold voltage domino gate. However, the gate oxide leakage is ignored in the previous studies. The significantly increased gate dielectric tunneling current, as described in this paper, shifts the leakage power characteristics of dynamic circuits in the sub-65nm CMOS technologies. Contrary to the previously published techniques in older technologies, a charged dynamic node voltage state with low inputs is preferred for reducing the total leakage power consumption in the wide fan-in dual threshold voltage domino gates. Similarly, a charged dynamic node voltage state with low inputs is preferred for lowering the leakage power consumption in all types of low threshold voltage domino gates in a 45nm CMOS technology

A high-to-low switching DC-DC converter that operates at input supply voltages up to twice the maximum voltage permitted in a nanometer CMOS technology is proposed. The circuit technique is based on a cascode bridge that maintains the steady-state voltage differences among the terminals of all of the transistors within a range imposed by a specific fabrication technology. The proposed circuit technique permits the full integration of active and passive devices of a switching DC-DC converter with a high voltage conversion ratio in a standard low voltage CMOS process. An efficiency of 87.8% is achieved for 3.6 V to 0.9 V conversion, assuming a 0.18 /spl mu/m CMOS technology. The DC-DC converter operates at a switching frequency of 97 MHz while supplying a DC current of 250 mA to the load.

The temperature dependent subthreshold and gate oxide leakage power characteristics of domino logic circuits are evaluated in this paper. The preferred input vectors and node voltage states that minimize the total leakage power consumption are identified at the lower and upper extremes of a typical die temperature spectrum. New low leakage circuit design guidelines are presented based on the results. The significantly increased gate dielectric tunneling current, as described in this paper, dramatically changes the leakage power characteristics of dynamic circuits in the sub-65nm CMOS technologies. Furthermore, the leakage power savings provided by the dual threshold voltage domino logic circuit techniques are all together reduced due to the significance of the gate dielectric tunneling in the nanometer CMOS technologies

The supply voltage to threshold voltage ratio is reduced with each new technology generation. The gate overdrive variation with temperature plays an increasingly important role in determining the speed characteristics of CMOS integrated circuits. The temperature dependent propagation delay characteristics, as shown in this paper, will experience a complete reversal in the near future. Contrary to the older technology generations, the speed of circuits in a 45 nm CMOS technology is enhanced when the temperature is increased at the nominal supply voltage. Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable operation under temperature variations. A design methodology based on optimizing the supply voltage for temperature variation insensitive circuit performance is presented in this paper. The optimum supply voltage is 45% to 57% lower than the nominal supply voltage in a 180 nm CMOS technology. Alternatively, the optimum supply voltage is 10% to 54% higher than the nominal supply voltage in a 45 nm CMOS technology. The gap between the optimum and nominal supply voltages increases in a low-power design. Deeply scaled low-power integrated circuits operating at ultra-low voltage supplies are, therefore, expected to be highly sensitive to temperature variations. Alternatively, the speed-centric determination of the supply voltage will be less catastrophic for maintaining the circuit reliability under temperature variations in the future technology generations

A new low voltage swing technique is presented in this paper for simultaneously reducing the active and standby mode power consumption and enhancing the noise immunity in domino logic circuits. The proposed circuit technique modifies both the upper and lower boundaries of the voltage swing at the dynamic node. Meanwhile, full voltage swing signals are maintained at the inputs and the outputs for high speed operation. The power supply and ground voltages are simultaneously optimized to minimize the power-delay product (PDP). The proposed technique reduces the PDP by up to 28% as compared to the standard full-swing circuits in a 45nm CMOS technology. The active mode power consumption is reduced by up to 32% due to the lower switching power required to charge/discharge the dynamic node. Furthermore, the noise immunity is enhanced by up to 59% as compared to the standard full-swing circuits. The bidirectional dynamic node low voltage swing technique also reduces the idle mode leakage power by up to 20% in the high fan-in domino gates. Furthermore, approximately a 3.9 times reduction in leakage power consumption is offered as compared to a previously published low swing domino logic circuit technique in a 45nm CMOS technology

A forward body biased keeper circuit technique is proposed in this paper for enhancing the robustness of dynamic circuits. The proposed circuit technique is evaluated as an alternative to the standard approach of increasing the physical size of a keeper transistor for enhanced noise immunity. The forward body biased keeper circuit technique has a lower speed penalty under the same noise immunity conditions as compared to a standard keeper sizing technique. The effectiveness of the proposed circuit technique can be further increased provided that the junction temperature is reduced using active cooling and refrigeration.

Rapidly increasing input current of microprocessors resulted in rising cost and motherboard real estate occupied by decoupling capacitors and power routing. We show by analysis that an on-die switching DC-DC converter is feasible for future microprocessor power delivery. The DC-DC converter can be fabricated in an existing CMOS process (90nm-180nm) with a back-end thin-film inductor module. We show that 85% efficiency and 10% output voltage droop can be achieved for 4:1, 3:1, and 2:1 conversion ratios, area overhead of 5% and no additional on-die decoupling capacitance. A 4:1 conversion results in 3.4x smaller input current and 6.8x smaller external decoupling.

A cascode bridge circuit for monolithic switching DC-DC converters operating at high input voltages is proposed in this paper. The proposed circuit can also be used as an I/O buffer to interface circuits operating at significantly different voltages. The circuit technique permits the full integration of the active and passive devices of a switching DC-DC converter with a high voltage conversion ratio in a standard low voltage CMOS technology. The cascode bridge structure guarantees the reliable operation of deep submicron MOSFETs without exposure to high voltage stress while operating at high input and output voltages. With the proposed circuit technique, steady-state voltage differences between the terminals of all of the MOSFETs in a switching DC-DC converter are maintained within a range imposed by a target low voltage CMOS technology. High-to-low DC-DC converters operating at input voltages up to three times as high as the maximum voltage that can be directly applied across the terminals of a MOSFET are described. An efficiency of 79.6% is achieved for 5.4 V to 0.9 V conversion, assuming a 0.18 /spl mu/m CMOS technology. The DC-DC converter operates at a switching frequency of 97 MHz while supplying a DC current of 250 mA to the load.

The design of an efficient monolithic buck converter is presented in this paper. A low swing MOSFET gate drive technique is proposed that improves the efficiency characteristics of a DC-DC converter. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is described which characterizes the integration of both active and passive devices of a buck converter onto the same die based on a 0.18 /spl mu/m CMOS technology. The optimum gate voltage swing of a power MOSFET that maximizes efficiency is shown to be lower than a standard full voltage swing. An efficiency of 88% at a switching frequency of 102 MHz is achieved for a voltage conversion from 1.8 volts to 0.9 volts with a low swing DC-DC converter. The power dissipation of a low swing DC-DC converter is reduced by 24.5%, improving the efficiency by 3.9% as compared to a full swing DC-DC converter.

A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of the keeper transistor is dynamically modified during circuit operation to reduce the contention current without sacrificing noise immunity. A four-bit multiple-output domino carry generator for a carry lookahead adder is designed with the proposed circuit technique. It is shown that the variable threshold voltage keeper circuit technique enhances the circuit evaluation speed by up to 60% while reducing power dissipation by 37% as compared to a standard domino logic circuit. It is also shown that the proposed domino logic circuit technique offers 20% higher noise immunity as compared to a standard domino circuit with the same evaluation delay characteristics.

A bi-directional CMOS voltage interface circuit is proposed for applications that require signal transfer between two circuits operating at different voltage levels. The circuit can also be used as a level converter at the driver and receiver ends of long interconnect lines for low swing applications. The operation of the voltage interface circuit is verified by both simulation and experimental test circuits. The proposed voltage interface circuit operates at high speed while offering significant power savings of up to 95% as compared to existing schemes.

A new circuit technique is proposed in this paper to lower the energy overhead of mode transitions for effective energy reduction with the MTCMOS circuits. The charge stored at the virtual rails and the sleep signal lines are recycled during the active-to-sleep-to-active mode transitions with the proposed technique. Applying the charge recycling MTCMOS circuit technique to a 32-bit Brent-Kung adder reduces the energy overhead due to the mode transitions by up to 12.2% as compared to the conventional MTCMOS circuits. Furthermore, the standby mode power consumption is reduced by up to 92.8% as compared to a standard Brent-Kung adder in a 65 nm CMOS technology.

A new circuit technique based on a single PMOS sleep transistor and a dual threshold voltage CMOS technology is proposed in this paper for simultaneously reducing subthreshold and gate oxide leakage currents in idle domino logic circuits. In the sleep mode, the output inverter and keeper transistor of a domino gate are disconnected from the power supply by turning off a high threshold voltage sleep switch. The dynamic and output nodes are discharged by the initially high subthreshold and gate oxide leakage currents produced by the NMOS transistors in the pull-down network, output inverter, and fan-out gates. After the node voltages settle, the circuit is placed into a low subthreshold and gate oxide leakage state. The effectiveness of the circuit technique for suppressing leakage current is verified under significant fluctuations of channel length, gate oxide thickness, and channel doping concentration due to process variations. The proposed circuit technique lowers the total leakage power by 67.7% to 98.8% as compared to standard dual threshold voltage domino logic circuits. Similarly, an 11.7% to 84.1% reduction in total leakage power is observed as compared to a previously published sleep switch scheme in a 45nm CMOS technology.

Multi-threshold voltage CMOS (MTCMOS) is an effective technique for reducing the leakage energy consumption of idle circuits. The MTCMOS circuits, however, suffer from high energy overhead during the transitions between the active and standby modes. The trade-offs between the mode transition energy overhead, the wake-up delay, and the standby mode power consumption of the MTCMOS circuits are evaluated in this paper. The short-circuit power consumed by an MTCMOS circuit during a wake-up event is characterized. Appropriate sleep signal buffer sizing guidelines to achieve sleep-to-active mode transitions with low energy overhead are provided. An optimum range of sleep transistor buffer sizes is identified for a 32-bit Brent-Kung MTCMOS adder in a 65 nm CMOS technology. It is shown that reducing the buffer size below the lower boundary of this optimum region is not effective for lowering the overall energy overhead and standby mode power consumption while causing a significant degradation in the wake-up speed.

In this paper, the supply and threshold voltage optimization techniques to achieve temperature variation insensitive circuit performance are compared. The speed and energy tradeoffs with the two optimization techniques are presented.

In the sub-65 nm CMOS technologies, subthreshold and gate dielectric leakage currents need to be simultaneously suppressed for effective energy reduction. New low-leakage circuit techniques based on multi-threshold-voltage (multi-Vt) and multi-oxide-thickness (multi-tox) standard single-gate and emerging double-gate MOSFET/FinFET technologies are presented in this paper. The leakage savings achieved with the techniques are characterized for a diverse set of logic and memory circuits that are widely used in systems-on-chips. The speed, active power, noise immunity, and area tradeoffs with the leakage reduction schemes are also evaluated.