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Slow tool servo (STS) turning is a superior process for machining precision and complicated surfaces that has already gained a wide application especially in optics industry. However, it is lack of systematically study of tool path generation for STS turning of complex surfaces, especially of interpolation among discrete cutting location points. This paper presents a comprehensive tool path generation strategy for STS turning of complex surfaces, including cutting location point optimized planning, trajectory interpolation, and machining simulation. First, cutting contact point discretization and tool geometry compensation were analyzed during cutting location point planning procedure. Second, Hermite segment interpolation used by trajectory interpolation was analyzed, and three position-velocity-time (PVT) entrance parameters algorithms were put forward, i.e., the constant speed method, area method, and the three points method. Third, the machining simulation was carried out to evaluate the performance of the generated tool path. The analysis of Z-axis motion characteristics indicated that both the area method ( c = 2/3) and three points method can meet the requirements of smooth velocity of Z-axis when the Z-axis reciprocating frequency is similar to the C-axis rotating frequency. From the viewpoint of acceleration, the three points method is much better than the area method when the Z-axis reciprocating frequency is significantly greater than the C-axis rotary frequency. Finally, a progressive addition lens surface was fabricated to prove the feasibility of the proposed tool path generation method. [ABSTRACT FROM AUTHOR]

Micro-features are frequently created on medical needles to improve the visibility and friction behavior in ultrasound-guided percutaneous procedures. Ultra-short pulsed laser ablation is the front runner among the current material micro-processing technologies. In this paper, the effect of process parameters in laser surface texturing (LST) of medical needles was studied by experiments based on Taguchi methodology. The evolution of ablation dimension and surface roughness with different process parameters was measured by optical microscope. Based on response surface regression, mathematical models for correlating the machined depth and surface roughness with the overlap and overscan number were developed. Analysis of variance (ANOVA) was carried out to access the adequacy of the developed mathematical models. The results indicate that the developed mathematical models can predict the machined depth and surface roughness during LST operation satisfactorily. Analyses were made to study the effect of the process parameters on the machined micro-channel. From the analysis, it was found that the overlap and overscan number have great influences on the machined depth and surface roughness. [ABSTRACT FROM AUTHOR]

A new technology assessment methodology is proposed to simultaneously evaluate circuit-level energy, delay, and yield under realistic device operation theme through Monte Carlo analysis. Given any yield constraints, this new methodology can maximize the circuit energy efficiency without overdesign. It provides a method to quantify the tradeoff between energy–delay (ED) and yield. The proposed method is proved to be efficient especially for low power circuit applications compared with ED-only approach. Taking 14-nm FinFET design, for example, the impacts of major variation sources are analyzed for different circuit applications, showing a different trend from the ED-only approach. In addition, the methodology is also extended to include the impacts of reliability issues. A desired design strategy is found to balance the design merits and circuit reliability. The proposed methodology is helpful for technology assessment and early stage circuit design and planning. [ABSTRACT FROM AUTHOR]

In this paper, we use an automated tool flow in a 14 nm CMOS fin-shaped field-effect transistor (FinFET)/ static random access memory (SRAM) simulation-based design-technology cooptimization (DTCO) including both process-induced and intrinsic statistical variabilities. A 22 nm FinFET CMOS technology is used to illustrate the sensitivity to process-induced fin shape variation and to motivate this paper. Predictive Technology Computer Aided Design (TCAD) simulations have been carried out to evaluate the transistor performance ahead of silicon. Draft-diffusion simulations calibrated to the ensemble Monte Carlo simulation results are used to explore the process and the statistical variability space. This has been enabled by the automation of the tool flow and the dataset handling. The interplay between the process and the statistical variability has been examined in details. A two-stage compact model strategy is used to capture the interplay between process and statistical variability. To close the DTCO loop, the static noise margin and write noise margin sensitivity to cell design parameters and variability in FinFET-based SRAM designs are studied in details. [ABSTRACT FROM AUTHOR]

Industrial alumina ceramics require high surface accuracy when assembled to critical components of devices, for which high-quality milling has become an integral process. To achieve high-quality milling of alumina ceramics efficiently, this paper introduced a composite strategy based on the sequence of roughing and finishing via the femtosecond laser burst-mode. Firstly, the effects of laser parameters in the single-pulse mode such as energy fluence, spot overlap ratio, and scanning spacing on the milling quality and efficiency of alumina ceramics were investigated to provide a basis of the parameter selection for the subsequent composite strategy study. Then, the influence of the burst-mode on the optimization of the milling results was discussed, and the advantages of this mode over the single-pulse mode were revealed. Finally, a comparative investigation on the processing performance between the composite strategy and the single strategy was carried out. The results showed that milling the same structure, the roughness of the groove was reduced by 10.69% compared to the optimal processing results in a single process. At the same time, the processing efficiency was maximized with an increase of 49.91%. [ABSTRACT FROM AUTHOR]

Abstract: Statistical variability and reliability due to random discrete dopants (RDD), gate line edge roughness (LER), metal gate granularity and N/PBIT associated random charge trapping has limited the progressive scaling of bulk planar MOSFETs beyond the 20-nm technology node. In this paper, their impacts on device figures of merit are studied through comprehensive 3-D simulation. It is found that raised drain-bias can exacerbate threshold-voltage fluctuations, mainly due to LER and RDD. Subthreshold slope (SS) variations resulting from each variation source is studied: RDD and LER generate most of the SS variation and are primarily responsible for its skew. Drain induced barrier lowering (DIBL) is examined against each intrinsic variation source, and RDD and LER are found to cause most of the DIBL variability. The correlation of DIBL with threshold-voltage is fully analysed with respect to each source of statistical variability and reliability. Except for LER, all major sources of variability exhibit de-correlation of DIBL against threshold-voltage. [Copyright &y& Elsevier]

In this paper, we compare results from atomistic and continuous simulation of decananometer scale CMOS transistors. We study the behavior of important figures of merit, including threshold voltage, subthreshold slope, OFF-current, and ON-current. We provide physical explanation for the origin of the discrepancies between the averaged values obtained from the statistical simulations and the results from the continuous doping simulation. Based on our analysis, we clearly demonstrate that there are increasing errors in the doping distributions when device TCAD simulations are calibrated using continuous doping profiles. This questions the use of continuous doping profiles in the routine calibration and TCAD-based optimization of decananometer scale CMOS transistors. [ABSTRACT FROM AUTHOR]

Background: In sepsis, the relationship between lymphocyte counts and patient outcomes is complex. Lymphocytopenia and lymphocytosis significantly influence survival, illustrating the dual functionality of lymphocytes in responding to infections. This study investigates this complex interaction, focusing on how variations in lymphocyte counts correlate with all-cause hospital mortality among sepsis patients. Methods: This retrospective cohort study analyzed data from two extensive critical care databases: the Medical Information Mart for Intensive Care IV 2.0 (MIMIC-IV 2.0) from Beth Israel Deaconess Medical Center, Boston, Massachusetts, and the eICU Collaborative Research Database (eICU-CRD), which was Multi-center database from over 200 hospitals across the United States conducted by Philips eICU Research Institute. We included adult patients aged 18 years and older who met the Sepsis-3 criteria, characterized by documented or suspected infection and a Sequential Organ Failure Assessment (SOFA) score of 2 or higher. Sepsis patients were categorized into quartiles based on lymphocyte counts. The primary outcome was all-cause mortality in the hospital, with 90 and 60-day all-cause mortality as the secondary outcomes. Univariable and multivariable Cox proportional hazard regressions were utilized to assess lymphocyte counts' impact on hospital mortality. An adjusted restricted cubic spline (RCS) analysis was performed to elucidate this relationship further. Subgroup analyses were also conducted to explore the association across various comorbidity groups among sepsis and septic shock patients. Results: Our study included 37,054 patients, with an observed in-hospital mortality rate of 16.6%. Univariable and multivariable Cox proportional hazard regression models showed that lymphocyte counts were independently associated with in-hospital mortality (HR = 1.04, P < 0.01; HR = 1.06, P < 0.01). RCS regression analysis revealed a U-shaped relationship between lymphocyte levels and hospital mortality risk in sepsis and septic shock patients (P for overall < 0.001, P for nonliner < 0.01; P for overall = 0.002, P for nonliner = 0.014). Subgroup analyses revealed that elevated lymphocyte counts correlated with increased hospital mortality among sepsis patients with liver disease and requiring renal replacement therapy (P for overall = 0.021, P for nonliner = 0.158; P for overall = 0.025, P for nonliner = 0.759). These findings suggest that lymphocytes may have enhanced prognostic value in specific subsets of critically ill sepsis patients. Conclusion: Our findings demonstrate that lymphocyte counts are a significant independent predictor of hospital mortality in sepsis and septic shock patients. We observed a U-shaped association between lymphocyte levels and mortality risk, indicating that high and low counts are linked to increased mortality. This result highlights the complex role of lymphocytes in sepsis outcomes and suggests the need for further investigation into the underlying mechanisms and potential therapeutic approaches. Integrating lymphocyte count assessment into risk stratification algorithms and clinical decision support tools could enhance the early identification of high-risk sepsis patients. [ABSTRACT FROM AUTHOR]

Comprehensive 3-D simulations have been carried out and compared with experimental data highlighting the dominant sources of statistical variability in 32-nm high-\kappa/\metal gate MOSFET technology. The statistical variability sources include random discrete dopants, line edge roughness, and metal gate granularity. Their relative importance is highlighted in the numerical simulations. Excellent agreement is achieved between the simulated and measured standard deviation of the threshold voltage. [ABSTRACT FROM PUBLISHER]