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The research problem of how to use a high-speed circuit switch, typically an optical switch, to most effectively boost the switching capacity of a datacenter network, has been extensively studied. In this work, we focus on a different but related research problem that arises when multiple (say s) parallel circuit switches are used: How to best split a switching workload D into sub-workloads $D_1, D_2, ..., D_s$, and give them to the s switches as their respective workloads, so that the overall makespan of the parallel switching system is minimized? Computing such an optimal split is unfortunately NP-hard, since the circuit/optical switch incurs a nontrivial reconfiguration delay when the switch configuration has to change. In this work, we formulate a weaker form of this problem: How to minimize the total number of nonzero entries in $D_1, D_2, ..., D_s$ (so that the overall reconfiguration cost can be kept low), under the constraint that every row or column sum of D (which corresponds to the workload imposed on a sending or receiving rack respectively) is evenly split? Although this weaker problem is still NP-hard, we are able to design LESS, an approximation algorithm that has a low approximation ratio of only $1+e$ in practice and a low computational complexity of only $O(m^2)$, where $m = \|D\|_0$ is the number of nonzero entries in D. Our simulation studies show that LESS results in excellent overall makespan performances under realistic datacenter traffic workloads and parameter settings.

Several representations have been proposed from last many years to represent Register Transfer Language (RTL). All description has their different level of success, views, design, and complexity. The primary objective of this paper is to provide a common platform or kernel to discuss all notation of register transfer language that can be described by particular representation. Register Transfer language is an abstraction of circuit switching and able to specify a hardware system from a very low level. The paper also presents the design and control of activities related to RTL. The RTL can be procedural and non-procedural in nature. The behavior of asynchronous control modules architecture has been discussed in further part of the paper. The next section deals with the application to design the complex systems using the register transfer language, instruction set architecture, and organization of the system. Remarks related to simulations, implementation automation capability of the system are given. Finally, the RTLs are analyzed concerning requirements, writing complexity, learning complexity and structural description of a hardware system.

Due to high efficiency and simple structure, LLC resonant converter is a promising topology for developing solid-state transformers. The heart of an LLC converter is the high frequency transformer that provides necessary insulation and step-up/down between primary and secondary sides. In addition, the efficiency of the transformer is a critical factor as it processes the entire power. This becomes even more challenging when circuit switching frequency is raised for shrinking passive component sizes, as skin effect and other non-ideal effects start to kick in. In solid-state transformer applications, size, efficiency and insulation have stringent specifications and meeting all requirements at once is not a simple task. Therefore, this paper presents multiple perspectives in terms of transformer design in an LLC converter and demonstrates with a 3-kW transformer capable of more than 15 kV insulation. Testing results show peak converter efficiency of 98.9% with transformer power density of 480 W/in3.

A main goal of the paper is to discuss the world telecommunications strategy in transition to the IP world. The paper discuss the shifting from circuit switching to packet switching in telecommunications and show the main obstacle is excessive software. As a case, we are passing through the three generations of American military communications: (1) implementation of signaling protocol SS7 and Advanced Intelligent Network, (2) transformation from SS7 to IP protocol and, finally, (3) the extremely ambitious cybersecurity issues. We use the newer unclassified open Defense Information Systems Agency documents, particularly: Department of Defense Information Enterprise Architecture; Unified Capabilities the Army. We discuss the newer US Government Accountability Office (2018) report on military equipment cyber vulnerabilities.

Reconfigurable/reprogrammable universal silicon photonic circuits represent a paradigm shift in designing photonic devices. However, it is very challenging to perform adaptive arbitrary reconfiguration when the high-dimensional solution of phase distribution cannot be explicitly determined, especially when there are random initial phase errors, which hinder the implementation of novel potential functions in universal circuits. This work presents an arbitrary black-box reconfiguration for universal circuits with random phase errors by a bacteria-foraging algorithm and unlocks a novel function of arbitrary-port-and-arbitrary-bit-resolution reconfigurable 6-bit photonic digital-to-analog conversion. This work offers a general and efficient method to ease multipurpose reconfiguration for universal silicon photonic circuits.

In order to meet the demand for highly scalable and energy efficient data center switches, multiplane architectures, where multiple optical switching domains are leveraged,\ud are an attractive solution. In this scenario, the orbital angular momentum (OAM) of light can be exploited as an additional domain along with wavelength, space, and time. In this\ud paper, we report the demonstration of an OAM-wavelength photonic integrated packet \ud witch controlled by a field-programmable gate array (FPGA) implementing a two-step scheduler suited for multiplane architectures. Packet-based bit error rate (BER) measurements show transmission at 20 Gb/s with BER

After an Introduction, the Chapter presents the sources of power dissipation in CMOS circuits, as well as a methodology for accurate power dissipation estimation using real-video data. State-of-the-art low-power techniques used in dedicated hardware accelerator designs are discussed in the next section. One of the methods introduced in this section shows the hybrid encoding of arithmetic operators and a new hybrid-encoded adder operator is presented. The power-efficient hybrid encoding representation groups m bit and uses gray encoding to potentially reduce circuit switching activity, both internally and at the inputs of the arithmetic operators. This section also discusses the exploration of different adder compressor structures in SAD operation and filter interpolation hardware architecture. Adder compressor architecture performs the simultaneous addition of N operands. Combinations of 3-2, 4-2, 5-2, and 7-2 adder compressors are discussed. An approximate computing technique is presented which is based on the coefficient pruning for SATD hardware architecture, and finally the application of the low-power techniques in SAD, SATD, and interpolation filters is presented in detail.

In spite of many advantages of hybrid electrical/optical datacenter networks (Hybrid-DCN), current job schedulers for data-parallel frameworks are not suitable for Hybrid-DCN, since the schedulers do not aggregate data traffic to facilitate using optical circuit switch (OCS). In this paper, we propose JobPacker, a job scheduler for data-parallel frameworks in Hybrid-DCN that aims to take full advantage of OCS to improve job performance. JobPacker aggregates the data transfers of a job in order to use OCS to improve data transfer efficiency. It first explores the tradeoff between parallelism and traffic aggregation for each shuffle-heavy recurring job, and then generates an offline schedule including which racks to run each job and the sequence to run the recurring jobs in each rack that yields the best performance. It has a new sorting method to prioritize recurring jobs in offline-scheduling to prevent high resource contention while fully utilizing cluster resources. In real-time scheduler, JobPacker uses the offline schedule to guide the data placement and schedule recurring jobs, and schedules non-recurring jobs to the idle resources not assigned to recurring jobs. Trace-driven simulation and GENI-based emulation show that JobPacker reduces the makespan up to 49% and the median completion time up to 43%, compared to the state-of-the-art schedulers in Hybrid-DCN.

The optical circuit switch (OCS) in recently proposed hybrid electrical/optical datacenter networks (Hybrid-DCN) can only be used to transfer large flows (i.e., flows with a large size of data). Current job schedulers for data-parallel frameworks are not suitable for Hybrid-DCN, since they neither place tasks to aggregate data traffic to take advantage of OCS nor schedule tasks to minimize the Coflow completion time (CCT). In this paper, we propose Co-scheduler, a job scheduler for dataparallel frameworks that aims to improve job performance by attempting to place the tasks of a job to aggregate enough data traffic to take advantage of OCS and minimize the CCT in Hybrid-DCN. Specifically, for each job, Co-scheduler computes a guideline on the number of racks to place the job's input data and to run the job's map tasks, so that the job can potentially take full advantage of OCS to transfer its data. When the map tasks of a job complete, Co-scheduler computes all the possible schedules of the reduce tasks of the job. Each possible schedule includes the number of racks to schedule the reduce tasks that enables the job to use OCS to transfer its data, and the number of reduce tasks to place on each of the racks that minimizes CCT of the job. Next, Co-scheduler selects a best schedule among all the possible schedules so that the job completion time is minimized. Finally, Co-scheduler schedules the map tasks and reduce tasks of the job based on the computed guideline and best schedule. The evaluation demonstrates that compared to the state-of-theart schedulers, Co-scheduler achieves performance improvements on makespan, average job completion time, and average CCT by up to 51.2%, 54.6% and 73.6%, respectively.

A main goal of the paper is to discuss the world telecommunications strategy in transition to the IP world. Particularly, we analyze the parallels between emergency and military services and co-existence of circuit switching and packet switching technologies. We discuss the difficulties to build the emergency networks in the U.S. and Russian Federation. As a case, we are passing through three generations of American military communications: (1) the implementation of signaling protocol SS7 and Advanced Intelligent Network, (2) transformation from SS7 to IP protocol and, finally, (3) the extremely ambitious cybersecurity issues. In conclusion, recalling the difficulties that complicate the transition from circuit switching, seems, it is timely to say: the long circuit switching CS and packet switching PS coexistence seems inevitable.

FiC (Flow-in-Cloud) is a multi-FPGA system to achieve monolithic large scale FPGA with across multiple FPGAs for computational-heavy applications. The FiC system employs multiple economical mid-range FPGAs and connect them directly with flexible and high bandwidth interconnection network. We developed FiCSW board as a 1st generation of FPGA board in the FiC project. The FiCSW design, since the FPGA is used as both computational resource and the network circuit switch, there are no host server for FPGA needed like other server-based multi FPGA architecture. This design strategy helps scalable FPGA fabric in low-cost. However, from the system manageability’s perspective, the strategy is hard to handle multiple FPGA nodes without management system. In this paper, we mainly focused on the management system on the FiCSW multi-FPGA system, introducing the system architecture and implementation, and working application on the FiCSW prototype system.

Optical interconnects are essential technologies for cloud computing and big-data processing on inter/intra data center networks. We present SDM-based optical networks using optical packet and circuit switching techniques to provide optical channels of diverse characteristics.

The deployment of Over-The-Top (OTT) Voice over IP (VoIP) applications has been accelerated after the adoption of high-speed communications technologies (e.g.: LTE) by mobile operators. Additionally, the high incurring costs imposed on subscribers who are roaming outside their Home Public Land Mobile Network (HPLMN) has also contributed to the widespread coverage of OTT VoIP. As a result, mobile operators are witnessing a dramatic drop on their Average Revenue per User (ARPU). Current OTT VoIP apps fail to interwork with circuit switched phone calls without compromising the security requirements imposed by regulators on MNOs. In this paper we propose a method that secures a competitive edge for mobile operators over current OTT VoIP apps. It bridges the CS with PS networks and provides full control by the operator while maintaining the same security requirements. Moreover, we propose an additional feature for enabling multi-device reachability through the subscriber’s phone number (MSISDN) which is provided by the mobile operator. The method’s implementation verifies that the system has little impact on the mobile operators infrastructure. We finally conclude by providing potential business models for MNOs to increase their ARPU and outperform OTT VoIP providers

This paper analyzes the performance of a commercially available wavelength-tunable laser for developing a large-scale (1,424 ×1,424) optical circuit switch intended for datacenter/HPC applications. The dynamic BER transitions of 100-Gbps DP-QPSK signals clarify the device feasibility.

FiC (Flow-in-Cloud) is a multi-FPGA system to realize a monolithic large FPGA image with multiple cost-efficient mid-range FPGAs connected with flexible and high bandwidth interconnection network. The FPGA is used as both for computational resource and the network circuit switch, and separating FPGA regions by partial reconfiguration (PR) design technique. In this paper, we will introduce the FPGA design methodology with the PR technique for the FiC system. Evaluation result shows that the proposed design methodology reduces design and configuration time, and it enables to replace the region for computation without stopping the network running on the same FPGA.

Transit networks are a set of intermediate connector systems responsible for forwarding long haul internetwork traffic. With the increase in network convergence across the globe, the available bandwidth in transit networks has become an issue of great significance. One of the solutions to this issue is the formulation of optical transit systems. This study proposes an effective and efficient networking solution to deal with the increase in transit networking traffic. Categorically, this research aims to formulate a mechanism to implement IP based Border Gateway Protocol (BGP) over Optical Circuit Switched (OCS) networks and a Routing and Wavelength Assignment (RWA) algorithm to maximize performance. Furthermore, the discussed design schematics have shown a significant drop in request blocking probability and an increase in carried load. The necessary calculations and analysis to maximize effectiveness have also been provided.

Medium voltage direct current (MVDC) distribution grids, that is proposed to improve power quality, enable high penetration of renewable sources, decrease operating losses, has drawn more and more attraction. However, dc faults ride-through remains to be a technical bottleneck constraining the extensive industry application of MVDC distribution grids, and the method based on DC circuit breaker (DCCB) is one of the most promising solution to deal with this problem. With features of no operating losses, low cost and free maintenance, the hybrid DCCB with current commutation drive circuit (CCDC) could be widely used in MVDC distribution system to interrupt DC fault current. During the current interruption process of DCCB with CCDC, circuit switching occurs twice, so the transient voltages are inevitable. In this paper, a simulation model of DCCB with CCDC is established by PSCAD, and the transient voltages are calculated. According to the simulation results, the transient voltages should be suppressed. Then, based on the mechanisms of the transient voltages, mitigation ways are proposed. In the end, the simulation results show that the transient voltages have been effectively suppressed and the reliability of DCCB with CCDC has been improved.

Data center networks are designed to interconnect large clusters of servers. However, their static, rack-based architecture poses many constraints. For instance, due to over-subscription, bandwidth tends to be highly unbalanced---while servers in the same rack enjoy full bisection bandwidth through a top-of-rack (ToR) switch, servers across racks have much more constrained bandwidth. This translates to a series of performance issues for modern cloud applications. In this paper, we propose a rackless data center (RDC) architecture that removes this fixed "rack boundary". We achieve this by inserting circuit switches at the edge layer, and dynamically reconfiguring the circuits to allow servers from different racks to form "locality groups". RDC optimizes the topology between servers and edge switches based on the changing workloads, and achieves lower flow completion times and improved load balance for realistic workloads.

Wireless networks are going through huge development due to growth in demand and supply of new wireless terminals having multiple features. Their application areas range from communication to infotainment and medical to gaming. Inclusion of large number of features make availability of sufficient power for long operational hours a key challenge in these devices. Hence, limited battery life of wireless terminals makes energy efficiency an important issue in wireless networks. Medium access control (MAC) protocols play an essential role in this context. In fact, MAC protocols can have a significant impact on energy consumption since both transmission and reception activities are very costly in terms of energy. A centralised polling based MAC avoids collisions and can guarantee a higher energy efficiency with respect to pure carrier sense multiple access (CSMA). Pointer controlled slot allocation and resynchronisation (PCSAR) protocol implements power conscious scheduling techniques to enable terminals enter prolonged sleep state, thereby improving the overall energy consumption of the network. This paper investigates the performance of PCSAR and compares it with the IEEE 802.11 standard infrastructure power save mode (PSM). Results demonstrate that PCSAR outperforms the standard mode in a composite rate WLAN scenario. Moreover, use of TDM based circuit switching makes PCSAR more reliable. These features make it a potentially good candidate for energy efficient reliable low latency communication for current (4G/LTE) and future (5G and beyond) applications.

4G Mobile communication system LTE is the recent 3GPP (3d generation partnership project) standard for Radio communications, it uses a full IP infrastructure and erase the older CS (Circuit Switched) systems by using only PS (Packet switched) in his EPC (Evolved Packet Core). This evolution posed a problem for operators to support Voice service in 4G LTE without depending on their 2G and 3G networks. 3GPP and GSMA (GSM Association) offered a wonderful solution for that to support voice over IP (VoIP), and that by installing an IMS (IP Multimedia Subsystem) infrastructure that offer voice service and connect LTE Network to it, we call that "VoLTE". Therefore, VoLTE is clearly the future of voice communications since it is over IP and it is compatible with NGN (Next Generation Network) in the fixed network part, also it can ensure a very good QoS (Quality of Service) because IP packet was designed to support high data throughput. This research paper analyzes the influence of link utilization and network congestion on end-to-end basis VoLTE performance. Different scenarios are simulated using LTE-Sim simulator tool in a good way. Finally, comparison among them is provided

We successfully demonstrate a transmission of a high layer split mobile interface for cell-less, high-speed train network applications using a commercially available XGS-PON. Operation is also demonstrated for a GbE interface.

This paper presents the integration of multiple silicon photonic (SiP) switches within a high-performance computing environment to enable network reconfigurability in order to achieve optimized bandwidth utilization. We demonstrate a physical testbed implementation that incorporates two fabricated SiP switches capable of switching traffic under real HPC benchmark workloads. The system uses dynamic optical bandwidth steering to match its physical network topology to the traffic characteristics of the application, and achieves up to approximately 40% reduction in application execution time of the high-performance computing benchmark. We present the detailed design of the network architecture and control plane of the system, and discuss the system performance improvements that arises from bandwidth-steering with silicon photonic-based circuit switching.

Spectrum is the most scarce resources for any mobile operator, with the exponentially growing demand for data services that require higher speeds [1], operators have to utilize the available spectrum in the most efficient way to provide the best data experience for smartphone users whom are hungry for data services, yet keep an adequate performance for circuit switched voice service for the legacy technologies in WCDMA and GSM that are still serving customers with handsets that are not supporting LTE. The advancement in clustering techniques could allow operator to optimize their network parameters in a more efficient way, so they can achieve better spectrum utilization for the legacy technologies that will allow more spectrum refarming for LTE needs.In this paper, we propose a new approach for optimizing GSM power control algorithm to enhance GSM voice performance in operators with limited spectrum allocated to this technology. The new approach has been tried in real mobile network with positive results in terms of voice quality and dropped call rate. The approach could be extended to other radio network algorithms to better exploiting current network resources.

A broad range of technologies have been developed for the chip and wafer scale connections and integrations of photonic and electronic circuits, although major challenges remain for achieving the single-functional-unit-level integration of electronic and photonic devices. Here we use field-effect transistor/light-effect transistor (FET–LET) hybrid 6T static random-access memory (SRAM) as an example to illustrate a novel approach that can alleviate three major challenges to the higher-level integration of the photonic and electronic elements: size mismatch, energy data rate, and cascadability. A hybrid 6T SRAM with two access FETs being replaced by LETs and the electrical word lines replaced by optical waveguides is proposed. This hybrid 6T SRAM is analyzed to reveal its potential in improvement of the switching speed and thus total energy consumption over the conventional 6T SRAM. Numerical analyses, for instance, for a prototype 64 kB hybrid SRAM array, show a factor of 4 and 22 reduction in read delay and read energy consumption, and 3 and 4 in write delay and write energy consumption, respectively, when the access FETs are replaced by LETs. The potential impacts on the peripheral and assist circuits due to this hybrid structure and application of the LETs there are also briefly discussed.

With the rapid spread of cloud-based services, intra-datacenter traffic is growing exponentially. In typical present datacenters, top-of-rack switches, which act as gateways to computer systems, are interconnected via multi-tier electrical-switching networks. The electrical switch necessitates costly optical-to-electrical and electrical-to-optical conversion. Furthermore, its power consumption will explode due to the ever-increasing intra-datacenter traffic. To handle the large volumes of traffic in a cost-effective manner, optical switches are expected to play a key role in future intra-datacenter networks. To realize such cost-effective networks, high-port-count optical circuit switches will be a critical component. High-port-count optical circuit switches can be used to construct a flat network, and we can reduce the dependence on costly multi-tier electrical-switching networks. In this tutorial paper, we overview high-port-count optical circuit switch architectures for future intra-datacenter networks and discuss their characteristics. The high-port-count switch can be attained by combining the different dimensions of space and wavelength.

Long short-term memory neural networks demonstrate a classification accuracy larger than 99% for highly variable and bursty, real-time server traffic flows. Their performance in terms of forecasting precision displays promising results, both for one-step as well as multi-step predictions. These capabilities make the a priori detection of heavy data streams possible, thus enabling the employment of optical circuit switching.

Optical circuit switching may be instrumental in meeting the cost, energy, and aggregate bandwidth requirements of future data center networks. However, conventional MEMS beam-steering cross-connects cannot provide submillisecond switching with the port count necessary for data centers. Here, we investigate a novel noncrossbar selector switch architecture and pupil-division switching layout to improve optical switching performance by relaxing the requirement of arbitrary switch configurability. This architecture and switch design enable MEMS beam-steering micromirrors to scale to microsecond response speeds while supporting high port count and low loss switching, and can realize a number of useful interconnection topologies. We present the design, fabrication, and experimental characterization of a proof-of-principle prototype using a single comb-driven MEMS mirror to achieve 150 μs switching of 61 ports between four preprogrammed interconnection mappings. We demonstrate the scalability of this switch architecture with a detailed optical design of a 2048-port selector switch with 20 μs switching time.

Flexible electronics with features of simple, low-cost, lightweight, recyclable, easily operable, and disposable are particularly desirable. Herein, a flexible fully-integrated self-powered system on paper was demonstrated by incorporating addressable paper circuit switch into potential-tunable foldable power paper. In which the electrode material as well as conducting interconnections, p-toluenesulfonic acid (p-TSA) doped polypyrrole embedded in-between the cellulose fibers (p-TSA-PPy/cellulose) were obtained by combining in-situ chemical oxidative polymerization with paper microfluidic technique. In such unique integrated configuration, the utilization of p-TSA-PPy/cellulose network not only dramatically enhanced the horizontal electrical conductivity, but also conquered the issue of vertical electroconductivity, allowing for the top-channel-bottom conductive interconnections. As a proof-of-concept, an all-paper microfluidic analytical platform that integrated paper-based electrochemiluminescence strategy and proposed power paper was constructed with comparable performance. This work greatly improves the understandings of all-paper-based self-powered systems, and presents the significant potential applications of paper-based flexible electronics.

Scaling the capacity while maintaining low latency and power consumption is a challenge for hierarchical data center networks (DCNs) based on electrical switches. In this work we present a novel all-optical flat DCN architecture OPSquare that potentially addresses the scaling issues by employing parallel intra-/inter-cluster switching networks, distributed fast WDM optical cross-connect (OXC) switches, and a novel top-of-rack (ToR) switch architecture. The fast (nanoseconds) WDM OXC switches allow flexible switching capability in both wavelength and time domains and statistical multiplexing. The OPSquare DCN performance targeting Petabit/s capacity has been thoroughly assessed. First the packet loss, latency, throughput, and scalability are numerically investigated under realistic data center traffic model. Results indicate that when scaling the DCN size up to 1024 ToR switches, a packet loss ratio below 10-6 and a server end-to-end latency lower than 2 μs can be guaranteed at load of 0.3 with limited 20 kB buffer. Then, the experimental evaluation of the DCN by employing 4 × 4 OXC prototypes shows multi-path dynamic switching with flow control operation. The case deploying 32 × 32 and 64 × 64 OXC switches connecting 1024 and 4096 ToRs are emulated and limited performance degradation has been observed. The potential of switching higher-order modulation and waveband signals further proves the suitability of OPSquare architecture for Petabit/s and low-latency DCN by using optical switches with moderate radix.

Scheduling algorithms are crucial for most existing switches to improve the throughput. However, the delay of the switching fabric cannot be guaranteed with such scheduling algorithms. This paper aims to design a novel load-balanced wire-speed multicast switching fabric along with the attractive merits of network coding. We adopt a two-phase self-routing switching fabric constructed by Boolean-multicast concentrators (SRBMCs), where the first SRBMC distributes the incoming cells to its outputs uniformly and the second allows the distributed cells to be self-routed and multicast to their destinations concurrently. To further improve the switching performance, linear network coding is smoothly combined with SRBMC to reduce the packet loss rate. Theoretical analysis and numerical simulation demonstrate that the proposed switching fabric cannot only achieve wire-speed multicast switching but also be recursively constructed into an indefinite large-scale one with such merits as no internal buffers, low complexity, and guarantee in switching delay. Finally, we implement the proposed fabric on Field-Programmable Gate Array and verify its performance in multicast switching.

Hybrid switching—in which a high bandwidth circuit switch (optical or wireless) is used in conjunction with a low bandwidth packet switch—is a promising alternative to interconnect servers in today’s large-scale data centers. Circuit switches offer a very high link rate, but incur a non-trivial reconfiguration delay which makes their scheduling challenging. In this paper, we demonstrate a lightweight, simple and nearly optimal scheduling algorithm that trades off reconfiguration costs with the benefits of reconfiguration that match the traffic demands. Seen alternatively, the algorithm provides a fast and approximate solution toward a constructive version of Carathéodory’s Theorem for the Birkhoff polytope. The algorithm also has strong connections to submodular optimization, achieves a performance at least half that of the optimal schedule and strictly outperforms the state of the art in a variety of traffic demand settings. These ideas naturally generalize: we see that indirect routing leads to exponential connectivity; this is another phenomenon of the power of multi-hop routing, distinct from the well-known load balancing effects. Keywords: Data center networks, Bridges and switches, Circuit networks, Network flows, Submodular optimization, Approximation algorithms, National Science Foundation (U.S.) (Grant CCF-1409106), National Science Foundation (U.S.) (Grant NeTS-1718270), United States. Army (Grant W911NF-14-1-0220)

Best Effort (BE) and Guaranteed Throughput services (GT) are the two broad categories of communication services provided in NoC. Few of the existing NoC architectures provide both of these services. GT based services, which are based on circuit switching or connection oriented mechanisms of packet switching, are usually preferred for real time traffic while packet switching services are provided by the BE architecture. In this paper, biologically inspired fault tolerant techniques are implemented on these two different services. Biologically inspired techniques offer novel ways of making NoCs fault tolerant; faults in NoCs arise partly due to advanced nanoscale manufacturing processes and the complex communication requirements of the processing elements (PEs). The proposed NoCs fault-tolerant methods (synaptogenesis and sprouting) are adapted from the biological brain's robust fault tolerant mechanisms. These techniques are implemented on both BE and GT services. From the experimental results, the BE architecture was efficiently utilizing the bandwidth compared to GT services, while throughput utilization of GT services were better. The accepted traffic (flit/cycle/node) of the BE architecture is 6.31% better than GT architecture while the accepted traffic of the bio-inspired techniques is 72.12% better than traditional fault tolerant techniques. Novel bio-inspired NoC fault tolerant techniques are proposed and implemented.Bio-inspired NoC fault tolerant technique using BE and GT architecture.Existing NoC architectures having BE and GT architecture.Existing NoC architectures and fault tolerance.

Chip multiprocessors (CMPs) require a low-latency interconnect fabric network-on-chip (NoC) to minimize processor stall time on instruction and data accesses that are serviced by the last-level cache (LLC). While packet-switched mesh interconnects sacrifice performance of many-core processors due to NoC-induced delays, existing circuit-switched interconnects do not offer lower network delays as they cannot hide the time it takes to set up a circuit. To address this problem, this work introduces CIMA—a hybrid circuit-switched and packet-switched mesh-based interconnection network that affords low LLC access delays at a small area cost. CIMA uses virtual cut-through (VCT) switching for short request packets, and benefits from circuit switching for longer, delay sensitive response packets. While a request is being served by the LLC, CIMA attempts to set up a circuit for the corresponding response packet. By the time the request packet is served and the response gets ready, a circuit has already been prepared, and as a result, the response packet experiences short delay in the network. A detailed evaluation targeting a 64-core CMP running scale-out workloads reveals that CIMA improves system performance by 21 percent over the state-of-the-art hybrid circuit-packet-switched network.

This paper reports on a novel ring-based data center architecture composed of multidimensional switching nodes. The nodes are interconnected with multicore fibers and can provide switching in three different physical, hierarchically overlaid dimensions (space, wavelength, and time). The proposed architecture allows for scaling in different dimensions while at the same time providing support for connections with different granularity. The ring topology reduces the number of different physical links required, leading to simplified cabling and easier link management, while optical bypass holds the prospect of low latency and low-power consumption. The performance of the multidimensional switching nodes has been investigated in an experimental demonstration comprising three network nodes connected with multicore fibers. Both high capacity wavelength connections and time-shared subwavelength connections have been established for connecting different nodes by switching in different physical dimensions. Error-free performance ( $\text{BER} ) has been achieved for all the connections with various granularity in all the investigated switching scenarios. The scalability of the system has been studied by increasing the transmission capacity to 1 Tbit/s/core equivalent to 7 Tbit/s total throughput in a single seven-core multicore fiber. The error-free performance ( $\text{BER} ) for all the connections confirms that the proposed architecture can meet the existing demands in data centers and accommodate the future traffic growth.

Optical integrated network (OIN) is a promising alternative to overcome the restrictions that electrical networks-on-chip (eNoCs) will face in the next generation of multiprocessor integrated systems due to electrical interconnects’ physical limitations. OINs present a higher bandwidth and lower power consumption but their full capabilities are curbed by high latency controllers. Control techniques, such as circuit switching, impose a high latency to perform the correct network routing and a better solution must be found in order to fully utilize OINs. In this letter, we have designed and modeled a low-latency centralized controller (LUCC). For validation purposes, we modeled different Mach–Zehnder interferometer (MZI)-based optical interconnects that employ the proposed LUCC. We obtain a response time of only one clock cycle when using the LUCC, even when conflicts are found.

It is often necessary to determine statistical parameters that characterize the quality of service on the network by managing when designing computer networks using the concept of virtual connections with bypass directions. In many ways, the attainable level of quality of the services provided is determined at the stage of network design, when decisions was made regarding the subscriber capacity of stations, the capacity of bundles of trunk lines, the composition and volume of telecommunication services provided. Despite constant progress in the field of network technologies, the problem of determining the necessary amount of network resources and ensuring the quality of user service remains relevant. In this regard, this article discusses a broadband digital network with service integration, based on an asynchronous network in which an iterative method implemented. Here the flow distribution is determined by the route matrix, and the load distribution between the nodes of each pair of nodes made through the path tree obtained on the matrix of routes when calculating this pair. At the same time, an algorithm has been built for allow optimal allocation of channel resources between circuit switching and packet switching subnets within an asynchronous network.

The Lightwave Energy-Efficient Datacenter (LEED) project within the ARPA-e ENLITENED program is developing novel energy-efficient multichannel lightwave networks. These networks are enabled by a new optical “rotor” switch that can reconfigure the network topology in less than 20 µs and a field-programmable-gate-array-based network interface controller called Corundum that can provide precise network-wide synchronization of packets admitted into the lightwave network. Here we review the optical networking research within LEED and discuss future directions.

Making optical circuit switching suitable for handling highly dynamic and profoundly changing traffic is a considerable challenge. This motivation drives the development of a hybrid electrical/optical network towards high bandwidth and low latency. Compared with the traditional non-aggregation scheme, we provide two machine learning assisted aggregation schemes. The first one is to design optical cross-connect switches to increase the throughput of the circuit-switched network. In this solution, the optical cross-connect serves both delay-sensitive traffic flows and delay-tolerant traffic flows. As the network throughput rises rapidly, the number of ports of the optical switch remains unchanged. The second scheme is to add small port counts, which maximizes throughput while relaxing the requirements for accurate machine learning algorithms. In this paper, we have a set of four machine learning algorithms, and only the most suitable one is selected at a time. We deploy a machine learning algorithm at edge nodes instead of a central network management system. Therefore, we can simultaneously reduce network overhead and latency. Both aggregation schemes outperform the traditional non-aggregation scheme in terms of throughput, delay, and flow completion time.

An online parameter-tuning method for the energy-efficient data center network (DCN) named HOLST (high-speed optical layer 1 switch system for time-slot-switching-based optical data center networks) is proposed. HOLST comprises an optical circuit switching network, optical slot switching network, and electrical packet switching network for the spine layer. It requires flows to be assigned to optimal switches to achieve high power savings. In this study, first we experimentally confirm that the change in the DCN characteristics in the short term of actual data center traffic downgrades the accuracy of flow classification. Subsequently, we propose a procedure for reconfiguring a flow classification function and a method for online parameter tuning for this function. Finally, the accuracy of the flow classification method using the proposed tuning and estimated switching energy consumption in the spine layer are evaluated. The proposed online parameter-tuning function increases the accuracy of flow classification and reduces switching energy consumption relative to the conventional flow classification function.