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This paper presents an integrated wireless system that helps a visually impaired person navigate within an indoor environment. The guidance process to help the person navigate uses a ZigBee wireless mesh network to localize the user and a compass to determine his/her orientation. The system uses a server to calculate an optimal path from the user's present location to the target location or item to be reached. The system receives voice commands from the visually impaired person and generates audio responses to guide the person. The mobile unit of the system is compact and requires relatively low power. Overall the system has minimal intrusion level and the results of various testing scenarios showed it was successful. The results also showed that the accuracy level depends on the available ZigBee modules within the mesh network and the particular zone.

Localization of sensor nodes is an important aspect in Wireless Sensor Networks (WSNs). This paper presents an overview of the major localization techniques for WSNs. These techniques are classified into centralized and distributed depending on where the computational effort is carried out. The paper concentrates on the factors that need to be considered when selecting a localization technique. The advantages and limitation of various techniques are also discussed. Finally, future research directions and challenges are highlighted.

A dual Time Delay Digital Tanlock Loop (D-TDTL) topology is proposed in this work. The system consists of a stacked dual loop of which the top one acts as a Frequency Lock loop (FLL) for the bottom loop, while the latter is a phase lock loop (PLL) that enhances the overall phase of the system. The main advantage of the proposed system is the large reduction of phase noise or jitter which makes it well suited to operate in noisy environment. The performance of the D-TDTL system was demonstrated using frequency shift keying (FSK) input signal with AWGN noise.

This paper focuses on an efficient technology for implementing a Mobile Agent System (MAS). The mobile agent is able to hold consumers' requests, migrates between platforms and executes its code autonomously. The agent is required to return results to its owner, so he or she can make the right decisions. Kerberos protocol is one of the best known authentication protocols based on symmetric key. Kerberos is a trusted third-party authentication protocol designed to establish network security. In this paper, we propose a new protocol that is based on enhancements modification of Kerberos and is suited to provide confidentiality, integrity, authentication and authorization. A security analysis of the new protocol is also provided.

Femtocell technology is expected to improve both coverage and capacity, especially indoors. Providers of cellular services are increasingly implementing this technology in their networks. However, the decentralized manner of femtocells operation introduces several challenges. This paper presents an overview of the femtocells. It highlights the network requirements for deploying femtocells and discusses the major issues that affect their operation and performance. The paper also describes the key challenges of deploying femtocells and some of the proposed solutions. It then presents the future direction on applying optimization to enhance femtocell performance.

Integration between multi-agents systems and mobile services can lead to advanced creative applications on smart handsets. Communication and learning are some of the main features of agents. These features can be utilized to implement a smart system that can be proactive and adaptive to a user's context/-situation. This paper highlights a number of related projects and points out their drawbacks. It proposes — an alternative architecture for a tourist guide system. It also describes the workflow of a number of tasks in the system and provides some possible scenarios regarding the use of such system.

This paper presents the design and simulation of an Auto-Gating technique for impulsive noise reduction in communication systems. The Auto-Gating process applies an adaptive approach in order to reduce the impact of impulsive noise. An AWGN system model that uses both 16-QAM and QPSK were implemented. The BER performance for the proposed technique under AWGN and impulsive noise was compared with different impulsive noise reduction techniques such as Fixed-Gating. The results showed that the proposed technique offered clear improvement over conventional techniques.

This work evaluates the bit error rate (BER) performance of various two-dimensional turbo product codes (TPCs). The turbo decoder is implemented using hard-input hard-output data, which is impaired by additive white Gaussian noise (AWGN) and multipath fading. The effectiveness of the iterative TPC BER is evaluated using sequential and non-sequential decoding. Numerical simulation for different TPCs have confirmed that the non-sequential decoding in Rayleigh fading channels can offer double the coding gain offered in AWGN channels. Moreover, the extra coding gain achieved by the non-sequential decoder is inversely proportional to the code rate and the code length.

This paper presents the architecture as well as the implementation of a system that helps blind person navigate independently within an enclosed environment such as the home. The system uses a wireless mesh network to provide the first level localization. It also incorporates additional components to provide more refined location and orientation information. Optimal path planning is done by a server that communicates wirelessly with the portable mobile unit that can be pushed by the blind person. The blind person issues commands and receives direction responses using audio signals.

In this paper the architecture of a second-order time delay digital tanlock loop (TDTL) with real-time adaptive calculation of the loop filter coefficients is proposed. An adaptive digital filter based on the recursive least squares (RLS) algorithm is used to generate the coefficients of the TDTL loop filter. This allows the filter coefficients to be continuously updated in real- time so as to optimise the noise immunity of the TDTL in a highly dynamic environment. The performance of the proposed system was evaluated and compared with the original TDTL system using both additive white Gaussian noise (AWGN) and Doppler shifts. The results indicate that the noise performance of the proposed system outperforms that of the original TDTL. (5 pages)

A new technique for fast error correction of the TDTL (time delay digital tanlock loop) is proposed. The technique is based on early comparison of the input signal frequency with that of the loop filter output. The result of this comparison is then used to select an optimum value for the loop filter output. This technique eliminates the need for continuously changing the loop filter coefficient. The major advantages of the proposed technique are a reduction in the complexity of the adaptive TDTL structure and an improvement in the loop acquisition time. The performance of the proposed system was tested using an FSK input signal and the results indicate enhanced performance compared to the conventional TDTL system.

This paper proposes two circuit topologies for acquisition enhancement in a time delay digital tanlock loop (TDTL). They are based on feedforward (FF) and feedback (FB) control schemes. Both schemes are used to improve the acquisition speed of the conventional TDTL by employing an auxiliary circuit. The ultimate objective of the FB and FF techniques is to control the damping ratio so as to prevent overshoot which may cause oscillations. However, the FF topology, with an adaptive threshold as opposed to a fixed threshold in the FB scheme, provides better control and improved response. The performance of the proposed FF and FB mechanisms have been investigated, under noise free conditions, by analysis and computer simulation and the results are presented. The results indicate that it is possible to bring the system into the steady state preventing continuous oscillations whenever the system is thrown outside the locking range.

This paper presents a novel design of a digital phase lock loop based on the digital tanlock loop (DTL) architecture. The new simplified design eliminates the requirement for a delay block. Instead, it incorporates an adaptation mechanism whose output feeds into the phase detector block of the new design and controls the acquisition time and locking range of the loop. The new proposed loop design was thoroughly tested and the results indicate that its overall performance compares favourably with that of the conventional time delay digital tanlock loop (TDTL).

An adaptive initialization process for the first-order time delay digital tanlock loop (TDTL) is proposed. The process results in improving the system performance by widening its lock range and by having zero steady-state phase error. The proposed adaptive TDTL with zero phase error (ATDTL-ZPE) uses a feedforward initialization technique which results in freeing the loop from the frequency locking process. The loop phase detector is used only for phase locking purposes and hence result in zero steady-state phase error with a considerable improvement in the system locking range.

This paper presents a second order time delay digital tanlock loop with improved locking as well as acquisition performance. The former is achieved through replacement of the delay unit of the TDTL by a variable one whose phase error is controlled by the output of the phase detector. This approach maintains the quadrature relationship between the two TDTL channels and hence results in a linearized phase detector characteristics. Fast acquisition is obtained through modification of the free running sampling frequency of digital controlled oscillator (DCO) in order to speed up the loop digital filter response. This improved architecture was tested using various input signals including FSK (frequency shift keying) and the results show an enhanced performance when compared with the original TDTL system.

This chapter presented some of the state of the art technologies and associated applications in the field of smart homes. It gave an overview of the major wireless communication technologies that form a fundamental part of the infrastructure of modern smart homes. Some of those technologies are integrated within sensing and networking devices such as Zigbee, Bluetooth, RFID, and WiFi. Other wireless technologies, such as the GSM, are more of a wider format that can form large network and yet can integrate with the other ones dedicated for short range. The paper also briefly discussed some of the modern sensors that can be used in smart homes. Many of them are of the embedded ubiquitous type that is equipped with wireless communication capabilities and can connect to other devices. The application areas discussed include appliances monitoring and control, safety and security, telehealth care, energy saving, environmental control, and information access.

This paper presents the design and implementation of an efficient sensor network (SN) over standard powerlines. As an application of the proposed SN, a home security and surveillance system was designed and implemented. The SN consists of a array of various types of security and surveillance sensors such as passive infrared motion detectors, glass/window break sensors, chemical/toxic gas sensors and smoke sensors. All the sensors will be connected to a gateway and a control panel through the pre installed powerlines. The gateway communicates with the sensors array using a medium access control (MAC) protocol which is created by combining the common Round Robin MAC and the Stop-and-Wait flow control protocol. The practical experiments conducted on the system have confirmed that the proposed design is robust, efficient and has several advantages over wireless and twistedpair wired sensor networks. The proposed network is implemented using the low-cost TDA5051A powerline modem and the 16F628A peripheral interface controller. 2010 IEEE. Scopus

This paper presents a time delay digital tanlock loop with a linearized phase detector (TDTL-LPD) architecture. This is achieved through replacement of the time delay unit of the TDTL by a variable delay whose phase error is controlled by a feedback mechanism driven by the output of the inverse tan phase detector. The change in this output is proportional to the changes in the input signal frequency of the system. This results in keeping the quadrature relationship between the two channels that make up the TDTL. This linearization of the phase error detector results in the improvement of the system performance when used in communication system applications such as FSK (frequency shift keying) demodulation.

This paper discusses various aspects of the design and implementation of the curriculum for three relatively closely related undergraduate engineering programs; namely communication, electronic, and computer engineering. A major distinctive feature of the programs is the emphasis on engineering projects carried out in groups and individually as well. The programs have strong technical focus and are embedded with integrated quality assurance measures, compared with conventional program structures that are offered by other institutions. The educational system is augmented with a multitude of mechanisms that enhance the teaching and learning process. The programs are accredited by both national and international bodies. The programs have proven to be very successful as graduates are well sought after by both industry and government.

This paper presents a new indirect frequency synthesizer based on a digital time delay tanlock loop. The loop used is a second order one and that results in a zero steady state error once the system is in lock. The process of locking the complete system following the introduction of the divider is achieved through the incorporation of a special adaptive locking mechanism. The adaptation block includes a finite state machine that eventually controls the loop digital filter and the digital controlled oscillator.

This paper describes a complete framework for an end- to-end smart home monitoring and control system. The communication with all components of the system is done using a variety of wireless technologies. The system incorporates security features at both ends that prevent unauthorized access as well as assign privileges to the users. The complete prototype smart home system was implemented and it supports three main services: monitoring the status of devices, controlling their settings through configurations that are device dependent, and periodic notification of the status of devices. The prototype system has a modular structure that enables the incorporation of additional components and services.

This paper presents practical design of a smart antenna system based on direction-of-arrival estimation and adaptive beamforming. Direction-of-arrival (DOA) estimation is based on the MUSIC algorithm for identifying the directions of the source signals incident on the sensor array comprising the smart antenna system. Adaptive beamforming is achieved using the LMS algorithm for directing the main beam towards the desired source signals and generating deep nulls in the directions of interfering signals. The smart antenna system designed involves a hardware part which provides real data measurements of the incident signals received by the sensor array. Results obtained verify the improved performance of the smart antenna system when the practical measurements of the signal environment surrounding the sensor array are used. This takes the form of sharper peaks in the MUSIC angular spectrum and deep nulls in the LMS array beampattern.

This paper presents a system with auto selection technique to reduce impulsive noise effect in wireless communication systems. The impulsive noise is detected through comparison with a fixed reference. The selection of the appropriate reduction technique to be applied is based on an estimation of the rate of impulsive noise occurrence. The proposed system uses subtraction-gating for low occurrence rate, conventional limiting for high occurrence rate, and passes the incoming signal to the output in the absence of impulsive noise. The results for QAM and FSK through simulation as well as real-time implementation on an FPGA development system are presented and show marked improvement in the bit error rate in each case.

An enhanced frequency synthesizer using a first order time delay tanlock loop (TDTL) is proposed in this work. Two adaptation mechanisms are introduced to improve the performance of the synthesizer. The first method compensates for the errors that resulted from the division process within the loop. The other adaptation technique is targeted at improving the locking performance of the loop. The later method is based on sensing the frequency at an earlier stage so that the error signal can be adapted for any frequency disturbance. The new developed synthesizer offers rapid acquisition and improved tracking performance over a wide locking range.

A frequency synthesizer using a first-order time delay tanlock loop (TDTL) is proposed in this work. The synthesizer involves introducing an integer divider within the structure of the TDTL in order to produce multiple frequencies from one reference source, which in the case of the TDTL is the Digital Controlled Oscillator (DCO). An adaptive mechanism was embedded into the loop to compensate for the errors and changes the divider will cause when it is introduced within the loop for different division factors.

This paper presents practical design of a smart antenna system based on direction-of-arrival estimation and adaptive beamforming. Direction-of-arrival estimation is based on the MUSIC algorithm for identifying the directions of the source signals incident on the sensor array comprising the smart antenna system. Adaptive beamforming is achieved using the LMS algorithm for directing the main beam towards the desired source signals and generating deep nulls in the directions of interfering signals. The smart antenna system designed involves a hardware part which provides real data measurements of the incident signals received by the sensor array. Results obtained verify the improved performance of the smart antenna system when the practical measurements of the signal environment surrounding the sensor array are used. This takes the form of sharper peaks in the MUSIC angular spectrum and deep nulls in the LMS array beampattern

This paper presents a study that compares the architectures and study’s the performance of some of the major integer multiplication algorithms. This is achieved through a simulation environment that at this stage implements four major multipliers in C++ programming language and implements the same architectures in an FPGA prototype system. The environment is a flexible one and has a well-designed user interface that makes it suitable for educational use. It enables the user to emulate the multipliers for various data inputs and observe the type of operation being executed. Handle-C was used for synthesis and subsequently implementation of the multipliers in an FPGA. The multipliers involved in this study are Hennessy, carry save, ripple carry array and Wallace tree. The performance of each multiplier is assessed through a study of its area and real-time complexities.

A non-uniform sampling Time Delay Digital Tanlock loop with an enhanced frequency acquisition performance is proposed in this work. An error detection circuitry is utilized to adjust the loop gain before the system goes out of the locking range. The process is controlled by a finite state machine. Through this adaptive process, the system can efficiently overcome frequency disturbances that may cause the loop to go out of lock. The performance of the proposed system under noise free conditions has been investigated by analysis and computer simulation. It is shown that the new developed loop can offer rapid acquisition and good tracking performance over a wide locking range.

In this work a time delay tanlock loop (TDTL) with an adaptive loop mechanism for faster acquisition and more reliable locking is proposed. The adaptive loop is designed to preserve the high SNR properties of the second order TDTL and overcomes its frequency locking limitation. This achieved by adjusting the loop digital filter coefficients and the digital controlled oscillator frequency when the system is subjected to large frequency disturbances that cause the loop to go out of lock. The sensing of the frequency disturbances and the adaptation process is automatically controlled by a finite state machine (FSM).

In the proposed work, an adaptive first order zero-crossing digital phase locked loop (AZC-DPLL) for rapid acquisition, reliable locking, and independent of input signal level is designed, simulated and subsequently implemented on an FPGA based reconfigurable system. The finite state machine controller of the AZC-DPLL senses any changes in input signal frequency and amplitude level, that may cause the loop to loose lock, and accordingly adjusts the loop gain to bring the loop in lock within a few samples. Through this adaptation process, the conflicting requirement of fast acquisition and reliable locking is achieved.

In this paper, a first order TDTL system is designed, simulated and implemented on a reconfigurable FPGA system. Initially the loop was designed and simulated using Matlab/Simulink. Subsequently some novel modifications were introduced to the TDTL in order to allow an optimized reconfigurable implementation, which eases the design process and allows for dynamic parameter and design modifications. The reconfigurable TDTL was tested in real time conditions under the same operating conditions of the simulated loop. Comparison between the simulated and real time results indicate a high degree of correlation, making the loop attractive for various practical applications.

In this work, the locking range and frequency acquisition characteristics of the time delay digital tanlock loop (TDTL) have been enhanced by adjusting the loop gain and the system time delay. These parameters are automatically controlled by a finite state machine. Through this adaptive process, the system can robustly overcome any frequency disturbances that may cause the loop to go out of lock. Simulation results of the new structure show that the newly developed loop can offer rapid acquisition and good tracking performance over a wide locking range. These new enhancements will allow the loop to be used in a wide range of signal processing applications.

This paper presents the design of an off-chip supply current monitor for the detection of faults in analogue circuits. The emphasis is placed on the design of a monitor with minimum overhead that can be implemented to detect variations in the dynamic supply current. The design of the monitor and the results of using it to detect faults in an analogue circuit, in both simulation and physical environments, are outlined.

This paper presents a study of the importance of analogue circuits testing in general and the challenges faced in testing these modules in a mixed-signal environment. It highlights the difficulties that are involved in testing analogue and mixed-signal circuits and compares them with those of testing digital only circuits. Sources of failure in integrated circuits and their relation to fault models are outlined. The paper concentrates on testing active analogue filter circuits operating in mid-range frequencies. A variety of filter circuits with different configurations and varied degrees of complexity are studied. Both soft and catastrophic single fault conditions are introduced to the circuits at the transistor, operational amplifier and feedback network levels. The work presented in the paper compares the detection of the injected faults using both frequency response and transient response voltage and current measurements. The objective is to determine the measurement method and parameter that is best at detecting a particular fault or class of faults. Analysis of the simulation data indicates that the measurement methods and parameters are complementary in terms of fault coverage and fault detection confidence.

The author presents a time-domain testing technique for analogue and mixed-signal circuits. The circuit-under-test (CUT) is simulated by a pseudo-random-binary sequence (PRBS) signal and both the voltage and supply current (Iddq) responses are measured. Both measurements are subsequently analyzed to detect the presence of a fault and to establish which measurement achieves higher confidence in the detection. The technique can test mixed-signal circuits in a unified manner and detecting soft and catastrophic faults. >

This paper presents the practical realisation of the transient response analysis proposed previously (1990, 1991) for the testing of mixed analogue/digital circuits. In this measurement system the circuit under test (CUT) is stimulated by a series of pulses in the form of a pseudo random binary sequence (PRBS). The transient response of the circuit is captured using a high speed analogue-digital converter and then transferred to a computer for subsequent signal analysis. The hardware system is described and results presented for both analogue and mixed signal circuits. >

This paper presents the design of a unified supply current monitor for the detection of faults in analogue circuits. The emphasis is placed on the design of a monitor with minimum overhead that can be implemented to detect variations in the dynamic supply current. The design of the monitor and the results of using it to detect faults in an analogue circuit in a simulation environment are outlined.

This paper outlines the problems of testing analog circuits in general and those in a mixed-signal integrated circuit in particular. It proposes a system level testing technique based on the excitation of the circuit-under-test with a pseudo-random binary sequence and subsequent estimation of its impulse response. The fault detection capability of the test and data analysis methods are demonstrated by simulation results. It also shows a feasible test structure that can be incorporated on chip to test the analog functions.

This paper presents a framework for monitoring internet traffic to detect the presence of hidden information in images that were subjected to steganography. The framework of steganalysis environment comprises three stages: pre-processing, statistical and distortion. The environment enables efficient steganalysis of internet traffic and gives an indication of the robustness of the various steganography techniques used in the study. An extensive set of cover images was used to set the detection thresholds. The impact of distortion, applied to destroy hidden information, was also assessed by calculating the cover image signal to noise ratio. The effectiveness of the complete environment as an integrated steganalysis system was evaluated by injecting a wide variety of clean as well as stegoed images that were not used during threshold setting. The results indicate that the integrated environment achieves a high detection rate with acceptable levels of false positive and false negative detections.

Smart homes are ones that have an intelligent environment that enables dynamic configuration of its devices as well as interaction with its occupants, be it while they are inside the home or remotely while outside. This paper outlines the major technologies that support the realisation of smart homes. It describes the complete architecture and design of a prototype smart home system that integrates a variety of wireless information and communication technologies with a variety of sensors and appliances. The prototype system enables an authorised user to monitor and control home devices equipped with a smart interface structure using a mobile phone. The system is embedded with authentication and verification mechanisms that provide secure end-to-end processing. The system is scalable through a flexible architecture that easily expands the portfolio of devices to be monitored and controlled.

Smart homes are intelligent environments that interact with their occupants in ways that improve their lives. This paper presents the ubiquitous pervasive technologies that will need to be integrated to realise the future vision of smart homes that have the intelligence to anticipate, predict and take decisions in a virtually autonomous manner. It also presents some of the major application areas that will benefit from the realisation of smart homes. It then discusses some of the challenges that need to be overcome in order for smart homes to become a reality and find acceptance from people across all sectors of the society.