492 results on '"Ortmanns, Maurits"'
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252. A novel optimization method for CT sigma-delta-modulators using a switched system model
253. A neural stimulator front-end with arbitrary pulse shape, HV compliance and adaptive supply requiring 0.05mm2 in 0.35μm HVCMOS
254. An 8mW 50MS/s CT ΔΣ modulator with 81dB SFDR and digital background DAC linearization
255. An AC-powered optical receiver consuming 270μW for transcutaneous 2Mb/s data transfer
256. A configurable cascaded continuous-time ΔΣ modulator with up to 15MHz bandwidth
257. High speed fully differential second generation current conveyor
258. Background DAC Error Estimation Using a Pseudo Random Noise Based Correlation Technique for Sigma-Delta Analog-to-Digital Converters
259. An Active Approach for Charge Balancing in Functional Electrical Stimulation
260. Hardware complexity of a correlation based background DAC error estimation technique for sigma-delta ADCs
261. Study on integrated transmission line ΣΔ modulators
262. A CMOS passive mixer for direct-conversion receivers
263. A differential Common-Gate Class-E Power Amplifier with positive-negative feedback
264. Experimental results on power efficient single-poly floating gate rectifiers
265. A background DAC error estimation in Sigma-Delta ADCs using a pseudo random noise based correlation technique
266. A Field Programmable Analog Array using floating gates for high resolution tuning
267. A Field-Programmable Analog Array of 55 Digitally Tunable OTAs in a Hexagonal Lattice
268. A Switchable Folded-Cascode OTA without Transmission Gates in the Signal Path
269. CMOS Integrated Active Rectifier with Temperature Independent Efficiency
270. DISCO: a graphical methodology for the design of Sigma-Delta modulators
271. Systematic approach to the synthesis of continuous-time cascaded sigma–delta modulators
272. A CMOS integrated voltage and power efficient AC/DC converter for energy harvesting applications
273. High efficiency, low-voltage and self-adjusting charge pump with enhanced impedance matching
274. A dynamic-Element-Matching architecture using individual element error shaping
275. Design of current reuse CMOS LC-VCO
276. A low-power differential common-gate LNA
277. A 0:5V rail-to-rail 1.5 μW CMOS amplifier for micro-energy harvesting applications
278. Optimized scheme for power-of-two coefficient approximation for low power decimation filters in sigma delta ADCs
279. Reliability study of single-poly floating gates in 0.13 μm CMOS for use in field programmable analog arrays
280. A hexagonal Field Programmable Analog Array consisting of 55 digitally tunable OTAs
281. A new optimization approach for the automatic design of ΣΔ-modulators
282. Analysis of digital gain error compensation in continuous-time cascaded sigma-delta modulators
283. High-bandwidth floating gate CMOS rectifiers with reduced voltage drop
284. Variability of flip-flop timing at sub-threshold voltages
285. A 232-Channel Epiretinal Stimulator ASIC
286. A Study on self-timed asynchronous subthreshold logic
287. An Unscented Kalman Filter for the estimation of circuit nonidealities with implicit decimation in continuous-time multibit Sigma-Delta modulators
288. A comparative study of CMOS LNAs
289. DISCO - A toolbox for the discrete-time simulation of continuous-time Sigma-Delta modulators using MATLAB™
290. Systematic approach to the synthesis of continuous-time cascaded Sigma-Delta modulators
291. A Method for the Discrete-Time Simulation of Continuous-Time Sigma-Delta Modulators
292. On the Implicit Anti-Aliasing Feature of Continuous-Time Multistage Noise-Shaping Sigma-Delta Modulators
293. Charge Balancing in Functional Electrical Stimulators: A Comparative Study
294. Estimating Circuit Nonidealities of Continuous-Time Multibit Delta-Sigma Modulators
295. A Continuous-Time Field Programmable Analog Array Using Parasitic Capacitance Gm-C Filters
296. Implementation and Analysis of Power Consumption for a Power Optimized Decimator Designed for Cascaded Sigma-Delta A/D Converters
297. Low power quantizer design in CT Delta Sigma modulators.
298. Analysis and design of high speed/high linearity continuous time delta-sigma modulator.
299. System level model for transcutaneous optical telemetric link.
300. A multi-channel neural stimulator with resonance compensated inductive receiver and closed-loop smart power management.
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