Search

A novel CMOS-compatible thin film SOI LDMOS with a novel body contact structure is proposed. It has a Si window and a P-body extended to the substrate through the Si window, thus, the P-body touches the P+ region to form the body contact. Compared with the conventional floating body SOI LDMOS (FB SOI LDMOS) structure, the new structure increases the off-state BV by 54%, decreases the specific on resistance by 20%, improves the output characteristics significantly, and suppresses the self-heating effect. Furthermore, the advantages of the low leakage current and low output capacitance of SOI devices do not degrade.

An analytical model for a novel high voltage silicon-on-insulator device with composite-k (relative permittivity) dielectric buried layer (CK SOI) is proposed. In this structure, the composite-k buried layer is composed by alternating Si3N4 and low-k (k = 2.65) dielectric in the lateral direction. Due to the composite-k buried layer, the breakdown voltage (BV) is improved both by the vertical and lateral direction. Taking the modulation effect of accumulated interface holes into account, an analytical model is developed. In the blocking state, the proposed model revealed the mechanism of hole accumulation above the Si3N4 buried layer and investigated the modulation effect of accumulated holes on the two-dimensional (2-D) potential and electric field distributions. This analytical model is verified by the simulation results. Compared with the low-k dielectric buried layer SOI (LK SOI), simulation results show that the BV for CK SOI is enhanced by 21% and the specific on-resistance is reduced by 32%, respectively.

A novel silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) with a high figure of merit (FOM) is proposed. The device features a double-sided charge oxide-trench (DCT) and a trench gate extended to the buried oxide. First, the oxide trench causes multiple-dimensional depletion in the drift region, which not only improves the electric field (E-field) strength, but also enhances the reduced surface field effect. Second, self-adaptive charges are collected in the DCT, which enhances the E-field strength of the trench oxide. Third, the oxide trench folds the drift region along the vertical direction, reducing the device cell pitch. Fourth, one side of the DCT regions acts as the body contact of p-well to reduce cell pitch and specific on-resistance (Ron,sp) further. Compared with a trench gate lateral double-diffused MOSFET, the DCT MOSFET increases the breakdown voltage (BV) from 53 V to 158 V at the same cell pitch of 3.5 μm, or reduces the cell pitch by 60% and Ron,sp by 70% at the same BV. The FOM (FOM=BV2/Ron,sp) of the proposed structure is 23 MW/cm2.

A high-k dielectric conduction enhancement SOI LDMOS is proposed and investigated by simulation. The high-k dielectric pillars are located at sidewalls of the drift region. The high-k dielectric assists the self-adapted depletion in the drift region, reshapes the electric field distribution, and makes the three-dimensional RESURF effect realized in a high-voltage blocking state. Dependences of the breakdown voltage (VB) and the specific on-resistance (Ron,sp) on device parameters are exhibited using three-dimensional simulation. Simulation results show that the proposed structure increases VB by 16%–18% and decreases Ron.sp by 13%–20%, compared with the conventional super-junction SOI LDMOS. Furthermore, the charge-imbalance caused by the substrate-assisted depletion effect is alleviated.

An SOI LDMOS with a compound buried layer (CBL) was proposed. The CBL consists of an upper buried oxide layer (UBOX) with a Si window and two oxide steps, a polysilicon layer and a lower buried oxide layer (LBOX). In the blocking state, the electric field strengths in the UBOX and LBOX are increased from 88 V/μm of the buried oxide (BOX) in a conventional SOI (C-SOI) LDMOS to 163 V/μm and 460 V/μm by the holes located on the top interfaces of the UBOX and LBOX, respectively. Compared with the C-SOI LDMOS, the CBL LDMOS increases the breakdown voltage from 477 to 847 V, and lowers the maximal temperature by 6 K.

An integrable silicon-on-insulator (SOI) power lateral MOSFET with a trench gate and a recessed drain (TGRD MOSFET) is proposed to reduce the on-resistance. Both of the trench gate extended to the buried oxide (BOX) and the recessed drain reduce the specific on-resistance (Ron,sp) by widening the vertical conduction area and shortening the extra current path. The trench gate is extended as a field plate improves the electric field distribution. Breakdown voltage (BV) of 97 V and Ron,sp of 0.985 mΩ·cm2 (VGS = 5 V) are obtained for a TGRD MOSFET with 6.5 μm half-cell pitch. Compared with the trench gate SOI MOSFET (TG MOSFET) and the conventional MOSFET, Ron,sp of the TGRD MOSFET decreases by 46% and 83% at the same BV, respectively. Compared with the SOI MOSFET with a trench gate and a trench drain (TGTD MOSFET), BV of the TGRD MOSFET increases by 37% at the same Ron,sp.

A low on-resistance (Ron,sp) integrable silicon-on-insulator (SOI) n-channel lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and its mechanism is investigated by simulation. The LDMOS has two features: the integration of a planar gate and an extended trench gate (double gates (DGs)); and a buried P-layer in the N-drift region, which forms a triple reduced surface field (RESURF) (TR) structure. The triple RESURF not only modulates the electric field distribution, but also increases N-drift doping, resulting in a reduced specific on-resistance (Ron,sp) and an improved breakdown voltage (BV) in the off-state. The DGs form dual conduction channels and, moreover, the extended trench gate widens the vertical conduction area, both of which further reduce the Ron,sp. The BV and Ron,sp are 328 V and 8.8 m??cm2, respectively, for a DG TR metal-oxide-semiconductor field-effect transistor (MOSFET) by simulation. Compared with a conventional SOI LDMOS, a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,Sp by 59% and increases BV by 6%. The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit, thereby saving the chip area and simplifying the fabrication processes.

An ultra-low specific on-resistance (Ron,sp) integrated silicon-on-insulator (SOI) double-gate triple RESURF (reduced surface field) n-type MOSFET (DG T-RESURF) is proposed. The MOSFET features two structures: an integrated double gates structure (DG) that combines a planar gate with an extended trench gate, and a p-type buried layer (BP) in the n-type drift region. First, the DG forms dual conduction channels and shortens the forward current path, so reducing Ron,sp. The DG works as a vertical field plate to improve the breakdown voltage (BV) characteristics. Second, the BP forms a triple RESURF structure (T-RESURF), which not only increases the drift doping concentration but also modulates the electric field. This results in a reduced Ron,sp and an improved BV. Third, the extended trench gate and the BP linked with the p-body region reduce the sensitivity of the BV to position of the BP. The BV of 325 V and Ron,sp of 8.6 m ??cm2 are obtained for the DG T-RESURF by simulation. Ron,sp of DG T-RESURF is decreased by 63.4% in comparison with a planar-gate single RESURF MOSFET (PG S-RESURF), and the BV is increased by 9.8%.

An ultra-low specific on-resistance ( R on,sp ) silicon-on-insulator (SOI) double-gate trench-type MOSFET (DG trench MOSFET) is proposed. The MOSFET features double gates and an oxide trench: the oxide trench is in the drift region, one trench gate is inset in the oxide trench and one trench gate is extended into the buried oxide. Firstly, the double gates reduce R on,sp by forming dual conduction channels. Secondly, the oxide trench not only folds the drift region, but also modulates the electric field, thereby reducing device pitch and increasing the breakdown voltage (BV). A BV of 93 V and a R on,sp of 51.8 mΩ·mm 2 is obtained for a DG trench MOSFET with a 3 μm half-cell pitch. Compared with a single-gate SOI MOSFET (SG MOSFET) and a single-gate SOI MOSFET with an oxide trench (SG trench MOSFET), the R on,sp of the DG trench MOSFET decreases by 63.3% and 33.8% at the same BV, respectively.

A new partial SOI (silion-on-insulator) (PSOI) high voltage P-channel LDMOS (lateral double-diffused metal-oxide semiconductor) with an interface hole islands (HI) layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field (EI) in the dielectric buried oxide layer (BOX) and modulate the electric field in drift region. This results in the enhancement of the breakdown voltage (BV). The values of EI and BV of an HI PSOI with a 2-μm thick SOI layer over a 1-μm thick buried layer are 580V/μm and −582 V, respectively, compared with 81.5 V/μm and −123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect (SHE). Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.

A novel triple RESURF (T-resurf) SOI LDMOS structure is proposed. This structure has a P-type buried layer. Firstly, the depletion layer can extend on both sides of the P-buried layer, serving as a triple RESURF and leading to a high drift doping and a low on-resistance. Secondly, at a high doping concentration of the drift region, the P-layer can reduce high bulk electric field in the drift region and enhance the vertical electric field at the drain side, which results in uniform bulk electric field distributions and an enhanced BV. The proposed structure is used in SOI devices for the first time. The T-resurf SOI LDMOS with BV D 315 V is obtained by simulation on a 6 m-thick SOI layer over a 2 m-thick buried oxide layer, and its Rsp is reduced from 16.5 to 13.8 mcm 2 in comparison with the double RESURF (D-resurf) SOI LDMOS. When the thickness of the SOI layer increases, T-resurf SOI LDMOS displays a more obvious effect on the enhancement of BV 2 /Ron. It reduces Rsp by 25% in 400 V SOI LDMOS and by 38% in 550 V SOI LDMOS compared with the D-resurf structure.

A low specific on-resistance (RS,on) silicon-on-insulator (SOI) trench MOSFET (metal—oxide—semiconductor—field—effect—transistor) with a reduced cell pitch is proposed. The lateral MOSFET features multiple trenches: two oxide trenches in the drift region and a trench gate extended to the buried oxide (BOX) (SOI MT MOSFET). Firstly, the oxide trenches increase the average electric field strength along the x direction due to lower permittivity of oxide compared with that of Si; secondly, the oxide trenches cause multiple-directional depletion, which improves the electric field distribution and enhances the reduced surface field (RESURF) effect in the SOI layer. Both of them result in a high breakdown voltage (BV). Thirdly, the oxide trenches cause the drift region to be folded in the vertical direction, leading to a shortened cell pitch and a reduced RS,on. Fourthly, the trench gate extended to the BOX further reduces RS,on, owing to the electron accumulation layer. The BV of the MT MOSFET increases from 309 V for a conventional SOI lateral double diffused metal—oxide semiconductor (LDMOS) to 632 V at the same half cell pitch of 21.5 μm, and RS,on decreases from 419 mΩcm2 to 36.6 mΩcm2. The proposed structure can also help to dramatically reduce the cell pitch at the same breakdown voltage.

A new SOI LDMOS structure with buried n-islands (BNIs) on the top interface of the buried oxide (BOX) is presented in a p-SOI high voltage integrated circuits (p-SOI HVICs), which exhibits good self-isolation performance between the power device and low-voltage control circuits. Furthermore, both the donor ions of BNIs and holes collected between depleted n-islands not only enhance the electric field in BOX from 32 to 113 V/μm, but also modulate the lateral electric field distribution, resulting in an improvement of the breakdown voltage of the BNI SOI LDMOS. A 673 V BNI SOI LDMOS is experimentally obtained and presents an excellent self-isolation performance in a p-SOI HVIC.

A novel partial silicon-on-insulator (PSOI) high voltage device with a low-k (relative permittivity) dielectric buried layer (LK PSOI) and its breakdown mechanism are presented and investigated by MEDICI. At a low k value the electric field strength in the dielectric buried layer (EI) is enhanced and a Si window makes the substrate share the vertical drop, resulting in a high vertical breakdown voltage; in the lateral direction, a high electric field peak is introduced at the Si window, which modulates the electric field distribution in the SOI layer; consequently, a high breakdown voltage (BV) is obtained. The values of EI and BV of LK PSOI with kI = 2 on a 2 μm thick SOI layer over 1 μm thick buried layer are enhanced by 74% and 19%, respectively, compared with those of the conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect.

A new SOI LIGBT (lateral insulated-gate bipolar transistor) with cathode- and anode-gates on partial membrane is proposed. A low on-state resistance is achieved when a negative voltage is applied to the anode gate. In the blocking state, the cathode gate is shortened to the cathode and the anode gate is shortened to the anode, leading to a fast switching speed. Moreover, the removal of the partial silicon substrate under the drift region avoids collecting charges beneath the buried oxide, which releases potential lines below the membrane, yielding an enhanced breakdown voltage (BV). Furthermore, a high switching speed is obtained due to the absence of the drain-substrate capacitance. Lastly, a combination of uniformity and variation in lateral doping profiles helps to achieve a high BV and low special on-resistance. Compared with a conventional LIGBT, the proposed structure exhibits high current capability, low special on-resistance, and double the BV.