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In this study, we explore the design of a subthreshold processor for use in ultra-low-energy sensor systems. We describe an 8-bit subthreshold processor that has been designed with energy efficiency as the primary constraint. The processor, which is functional below Vdd=200 mV, consumes only 3.5 pJ/inst at Vdd=350 mV and, under a reverse body bias, draws only 11 nW at Vdd=160 mV. Process and temperature variations in subthreshold circuits can cause dramatic fluctuations in performance and energy consumption and can lead to robustness problems. We investigate the use of body biasing to adapt to process and temperature variations. Test-chip measurements show that body biasing is particularly effective in subthreshold circuits and can eliminate performance variations with minimal energy penalties. Reduced performance is also problematic at low voltages, so we investigate global and local techniques for improving performance while maintaining energy efficiency.

Subthreshold circuit design is promising for future ultralow-energy sensor applications as well as highly parallel high-performance processing. Device scaling has the potential to increase speed in addition to decreasing both energy and cost in subthreshold circuits. However, no study has yet considered whether device scaling to 45 nm and beyond will be beneficial for subthreshold logic. We investigate the implications of device scaling on subthreshold logic and SRAM and And that the slow scaling of gate-oxide thickness leads to a 60% reduction in Ion/Ioff between the 90- and 32-nm device generations. We highlight the effects of this device degradation on noise margins, delay, and energy. We subsequently propose an alternative scaling strategy and demonstrate significant improvements in noise margins, delay, and energy in sub-Vth circuits. Using both optimized and unoptimized subthreshold device models, we explore the robustness of scaled subthreshold SRAM. We use a simple variability model and find that even small memories become unstable at advanced technology nodes. However, the simple device optimizations suggested in this paper can be used to improve nominal read noise margins by 64% at the 32-nm node.

This paper presents on-chip temperature sensor circuits for dense thermal monitoring in digital VLSI systems. The sensor directly captures the temperature dependency of threshold voltage. The prototype in a 65nm demonstrates that as compared to the state of the arts it can achieve a 9× smaller footprint of 30.1μm2 and a 3× smaller 3σ-error of

Online unsupervised spike sorting or clustering is an integral component of implantable closed-loop brain-computer-interface systems. Robust clustering performance against various non-idealities such as poor initialization and order-of-arrival of inputs are desirable while meeting the minimal area and power requirements for implants. We explore an online and unsupervised spike-sorting algorithm utilizing a low-overhead feature screening process that improves feature discriminability in the use of sub-optimal features for reducing hardware complexity. Based on the algorithm, an accelerator architecture that performs feature screening and clustering is devised and implemented in a 65-nm high-V TH CMOS, largely improving clustering accuracy even with poor clustering initialization. In the post-layout static timing and power simulation, the power consumption and the area of the accelerator are found to be 2.17 µW/ch and 0.052 µm2/ch, respectively, which are 53% and 25% smaller than the previous designs, while achieving the required throughput of 420 sorting/s at the supply voltage of 300mV.

We investigate two important performance-enhancing techniques - pipelining and parallelism - in the context of ultra-low voltage digital circuits. The investigation at near and sub-Vt supply voltages shows that pipelining can provide a superior benefit in throughput and energy-efficiency across a wide range of near and sub-Vt supply voltages while parallelism can provide a less amount of benefits only if the utilization of the circuits is high. Based on this investigation, an FFT core has been designed employing (1) an extensive degree of pipelining and (2) the parallelism with maximal utilization in major building blocks. The developed core demonstrates a significant amount of improvement in energy-efficiency and throughput over the existing near/sub-Vt FFT demonstrations.

In this paper, we propose a fine-grained many VT design methodology for ultra low voltage (ULV) operations of CMOS VLSI circuits. The fine-grained many VT transistors can be developed through only layout-level technique (e.g. inverse narrow width effects) in a multi-VT technology without any process modifications. Through SPICE simulations, we confirm that the proposed design methodology can improve performance, energy efficiency and variability of ULV circuits in three important domains, i.e. driving a fixed capacitive load, reducing active leakage energy consumption in non-critical paths, and lengthening short delay paths without energy overhead to aid error detection and correction techniques.

In this paper, we propose several design approaches to extend useful voltage scaling (i.e. voltage scaling with net energy savings) beyond the conventional limit, which is imposed by the rapid increase of leakage energy overhead in ultra low voltage regimes. We are able to achieve such extra voltage scaling and thus energy savings without compromising performance and variability through minimizing the ratio of leakage to dynamic energy in a circuit. Novel design approaches in pipeline, clocking and architecture optimization are investigated; and applied during the design of a 16b 1024pt complex FFT core. The measurement results from the prototyped FFT core in a 65nm CMOS show the energy consumption of 15.8nF/FFF with the clock frequency of 30MHz and the throughput of 240Msamples/s at the supply voltage of 270mV, which exhibits 2.4× higher energy efficiency and >10× higher throughput than the previous low power FFT designs. Measurement of 60 dies shows modest frequency and energy σ/μ spreads of 7% and 2%, respectively.

This paper investigates pipelining methodologies for the ultra low voltage regime. Based on an analytical model and simulations, we propose a pipelining technique that provides higher energy efficiency and performance than conventional approaches to ultra low voltage design. Two-phase latch based design and sequential circuit optimizations are also proposed to further improve energy efficiency and performance. Silicon results demonstrate a 16b multiplier using the approaches in 65nm CMOS improve energy efficiency by 30% and performance by 60%.

This paper proposes an ultra low energy FFT processor suitable for sensor applications. The processor is based on R4MDC but achieves full utilization of computational elements. It has two parallel datapaths that increase throughput by a factor of 2 and also enable high memory utilization. The proposed design is implemented in 65nm CMOS technology and post-layout simulation including parasitic capacitances shows it achieves 9.25x higher energy efficiency than state-of-the-art FFT processors and high throughput relative to past subthreshold circuit implementations.

A low leakage memory is an indispensable part of any sensor application that spends significant time in standby (sleep) mode. Although using high V th (HVT) devices is the most straightforward way to reduce leakage, it also limits operation speed during active mode. In this paper, a low leakage 10T SRAM cell, which compensates for operation speed using a readily available secondary supply, is proposed in a 0.18µm CMOS process. It achieves the lowest-to-date leakage power consumption and achieves robust operation at low voltage without sacrificing operation speed. The 10T SRAM has a bitcell area of 17.48µm2 and is measured to consume 1.85fW per bit at 0.35V.

A digitally trimmable voltage reference is proposed, achieving a tight distribution of temperature coefficient and output voltage, along with pA-range current consumption for V dd =0.5–3.0V. Using 2 temperature point digital trimming, the temperature coefficient and nominal output voltage are within 5.3–47.4ppm/°C and 175.2–176.5mV across 25 dies in 0.13μm CMOS. Non-trimmable versions are also implemented in 0.13µm and 0.18µm technologies to study process variations across multiple runs and technology portability of the design.

Robust design is a critical concern in ultra-low voltage operation due to large sensitivity to process and environmental variations. In particular, clock networks need careful attention to ensure robust distribution of well-defined clock signals to avoid setup and hold time violations. In this paper, we investigate the design methodology of robust clock networks for ultra-low voltage applications. A case study shows that an optimally-chosen clock network improves skew variation by 36× and energy consumption by 49%, compared to a typical clock network. Additionally, the impact of supply voltage and technology scaling on the optimal clock network construction is investigated.

A voltage reference using a depletion-mode device is designed in a 0.13µm CMOS process and achieves ultra-low power consumption and sub-1V operation without sacrificing temperature and supply voltage insensitivity. Measurements show a temperature coefficient of 19.4ppm/° (3.4 µV/°), line sensitivity of 0.033%/V, power supply rejection ratio of−67dB, and power consumption of 2.2pW. It requires only two devices and functions down to V dd =0.5V with an area of 1350µm2. A variant for higher Vout is also demonstrated.

Ubiquitous sensing systems, with a single node or thousands of nodes, are quickly becoming a viable technology option with the advancement of circuit and sensor design. In such a system, the most basic building block is an inexpensive sensor node with data processing and storage, off-chip communication, sensing elements, and a power source all linked within a robust package ideally with a volume on the order of lmm'. The sensor node must have a lifetime on the order of months or years. Due to the limitations of power sources, the most pressing implication of this lifetime requirement is that the power consumption of all components must be minimized.

Standby power can dominate the power budgets of battery-operated ultra-low power processors, and reducing standby power is the key challenge for further power reduction. State-of-the-art ultra low voltage sensors consume hundreds of nW in wake mode and 100 pW or less in standby mode. Therefore, applying known circuit techniques for further standby power reduction is very challenging. In this paper, we extend known standby power reduction techniques for use in ultra-low power processors. In particular, we propose structures that enable the use of super cut-off voltages throughout the design with minimal power overhead. Different strategies for power gated logic blocks and memory cells are investigated.

SRAM dominates standby power consumption in many systems since the power supply cannot be gated as in logic blocks. The use of ROM for parts of instruction memory can alleviate this power bottleneck in mobile sensing applications such as implantable biomedical and environmental sensing systems, which can spend up to 99% of their lifetimes in standby mode. However, robust ROM design becomes challenging as the supply voltage is reduced aggressively. In this paper, three different ROM topologies are investigated and compared for ultra-low voltage operation. A simple method to estimate the theoretical robustness at low voltage is proposed and applied to the ROM topologies. A test circuit fabricated in a carefully-selected 0.18 mum CMOS technology reveals that our proposed static NAND ROM structure improves performance by 26X, energy by 3.8X and lowest functional supply voltage by 100 mV over a conventional dynamic NAND ROM.

An integrated platform for sensor applications, called the Phoenix Processor, is implemented in a carefully-selected 0.18 mum process with an area of 915 times 915 mum2, making on-die battery integration feasible. Phoenix uses a comprehensive sleep strategy with a unique power gating approach, an event-driven CPU with compact ISA, data memory compression, a custom low leakage memory cell, and adaptive leakage management in data memory. Measurements show that Phoenix consumes 29.6 pW in sleep mode and 2.8 pJ/cycle in active mode.

Ultra Low voltage operation has recently drawn significant attention due to its large potential energy savings. However, typical design practices used for super-threshold operation are not necessarily compatible with the low voltage regime. Here, radically different guidelines may be needed since existing process technologies have been optimized for super-threshold operation. We therefore study the selection of the optimal technology in ultra low voltage designs to achieve minimum energy and minimum variability which are among foremost concerns. We investigate five industrial technologies, from 250 nm to 65 nm. We demonstrate that mature technologies are often the best choice in very low voltage applications, saving as much as ~1800X in total energy consumption compared to a poorly selected technology. In parallel, the effect of technology choice on variability is investigated, when operating at the energy optimal design point. The results show up to a 4X improvement in delay variation due to global process shift and mismatch when using the most advanced technologies despite their large variability at nominal Vdd.

A robust, energy efficient subthreshold (sub-Vth) processor has been designed and tested in a 0.13 mum technology. The processor consumes 11 nW at Vdd = 160 mV and 3.5 pJ/inst at Vdd = 350 mV. Variability and performance optimization techniques are investigated for sub-Vth circuits.

Subthreshold circuit design is a strong candidate for use in future low power applications. It is not clear, however, that device scaling to 45 nm and beyond will be beneficial in subthreshold circuits. We investigate the implications of device scaling on subthreshold circuits and find that the slow scaling of gate oxide thickness leads to a 60 % reduction in Ion/Ioff between the 90 nm and 32 nm device generations. We highlight the effects of this device degradation on noise margins, delay, and energy. We subsequently propose an alternative scaling strategy and demonstrate significant improvements in noise margins, delay, and energy in sub-Vth circuits.

Subthreshold operation is a promising method for reducing power consumption in ultra-low power applications, such as active RFIDs and sensor networks. It was shown in previous works that operating at the Vmin supply voltage results in optimal energy operation, where Vmin typically falls below the threshold voltage. However, all previous subthreshold analyses ignore the leakage current in standby mode. Hence, for applications where operation at Vmin results in completion of the task well ahead of the required deadline, the energy consumption can be significantly under-estimated. In this paper, we investigate the effect of the non-zero standby energy on the optimal energy consumption in subthreshold operation. We first analyze energy consumption both with and without a cutoff technique in standby mode. Two parameters are proposed to capture the cutoff structure's effect on the energy consumption. Second, a methodology to minimize the total energy consumption is addressed. The selection of the cutoff structure is examined by comparing three different structures. Then, a co-optimization method to optimize the size of the cutoff structure concurrently with the supply voltage, is proposed. This approach reduces energy by 99.2% compared to standby-energy-unaware optimization.

This paper presents an ultra-low-power voice activity detector (VAD). It uses analog signal processing for acoustic feature extraction (AFE) directly on the microphone output, approximate event-driven analog-to-digital conversion (ED-ADC), and digital deep neural network (DNN) for speech/non-speech classification. New circuits, including the low-noise amplifier, bandpass filter, and full-wave rectifier contribute to the more than 9 $\times $ normalized power/channel reduction in the feature extraction front-end compared to the best prior art. The digital DNN is a three-hidden-layer binarized multilayer perceptron (MLP) with a 2-neuron output layer and a 48-neuron input layer that receives parallel event streams from the ED-ADCs. To obtain the DNN weights via off-line training, a customized front-end model written in python is constructed to accelerate feature generation in software emulation, and the model parameters are extracted from Spectre simulations. The chip, fabricated in 0.18- $\mu \text{m}$ CMOS, has a core area of 1.66 $\times $ 1.52 mm2 and consumes 1 $\mu \text{W}$ . The classification measurements using the 1-hour 10-dB signal-to-noise ratio audio with restaurant background noise show a mean speech/non-speech hit rate of 84.4%/85.4% with a 1.88%/4.65% 1- $\sigma $ variation across ten dies that are all loaded with the same weights.

We present our recent progress in ultra-low-power intelligent acoustic sensing that harnesses the high power and energy efficiency of cochlea-like analog feature extraction and binarized neural network classification. Compared with conventional methods including the fast Fourier transform-based feature extraction plus neural network classification, and the more aggressive approach based on end-to-end neural network models, the analog filter bank-based handcrafted feature extraction inspired by mammalian cochlea has the promise of achieving the minimum power consumption for many existing and emerging always-on audio applications. System considerations and circuit techniques that are used to achieve the high power efficiency will be presented and comparison with some state-of-the-art works, and future directions will be discussed.