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The paper proposes a novel high-level approach for implementation-independent generation of functional software-based self test programs for processors with RISC architectures. The approach enables fast generation of manufacturing tests with high stuck-at fault coverage. The main concept of the method is based on separate test generation for the control and data parts of the high-level functional units. For the control part, a novel high-level control fault model is introduced whereas for the data part, pseudo-exhaustive test approaches can be applied to keep the independence from the implementation details. For the control parts, a novel high-level fault simulation method is proposed for evaluating the high-level fault coverage. The approach can be used for easy identification of redundant gate-level faults in the control part. The redundant faults can be identified by simple gate-level fault simulation of the generated high-level test when implementation is available. Experimental results of test generation for different units of a RISC processor support the solutions presented in the paper. [ABSTRACT FROM AUTHOR]

The recent advancements in the implementation technologies have brought to the front a wide spectrum of new defect types and reliability phenomena. The conventional design techniques do not cope with the integration capacity and stringent requirements of today's nanometer technology nodes. Timing-critical paths analysis is one of such tasks. It has applications in gate-level reliability analysis, e.g., Bias Temperature Instability (BTI) induced aging, but also several others. In this paper, we propose a fast simulation based technique for explicit identification of true timing-critical paths in both combinational and sequential circuits to enable reliability mitigation approaches, like selecting the paths for delay monitor insertion, resizing delay critical gates or applying rejuvenation stimuli. The high scalability of the method is achieved by using a novel fast method for finding activated paths for many test patterns in parallel, a novel algorithm to determine only a small subset of critical paths, and a novel method for identifying the true critical paths among this subset, using branch and bound strategy. The paper demonstrates efficient application of the proposed technique to gate-level NBTI-critical paths identification. The experimental results prove feasibility and scalability of the technique. [ABSTRACT FROM AUTHOR]

The Negative Bias Temperature Instability (NBTI) phenomenon is agreed to be one of the main reliability concerns in nanoscale circuits. It increases the threshold voltage of pMOS transistors, thus, slows down signal propagation along logic paths between flip-flops. NBTI may cause intermittent faults and, ultimately, the circuit's permanent functional failures. In this paper, we propose an innovative NBTI mitigation approach by rejuvenating the nanoscale logic along NBTI-critical paths. The method is based on hierarchical identification of NBTI-critical paths and the generation of rejuvenation stimuli using an Evolutionary Algorithm. A new, fast, yet accurate model for computation of NBTI-induced delays at gate-level is developed. This model is based on intensive SPICE simulations of individual gates. The generated rejuvenation stimuli are used to drive those pMOS transistors to the recovery phase, which are the most critical for the NBTI-induced path delay. It is intended to apply the rejuvenation procedure to the circuit, as an execution overhead, periodically. Experimental results performed on a set of designs demonstrate reduction of NBTI-induced delays by up to two times with an execution overhead of 0.1 % or less. The proposed approach is aimed at extending the reliable lifetime of nanoelectronics. [ABSTRACT FROM AUTHOR]

A new method is presented for simulating of Transition Delay Faults (TDF) based on the parallel exact critical path tracing for Stuck-at Fault (SAF) analysis and subsequent TDF reasoning. A method is proposed to extend the TDF model, traditionally considered as a class of robustly tested delay faults, to a class of TDFs with extended detection conditions. Three known fault classes of delay fault sensitization are considered: robust, non-robust and functional sensitization of delay faults. Additionally, a new fourth fault class is introduced, called non-robust functionally sensitized delay fault. A novel fault analysis algorithm based on 7-valued algebra is presented, which delivers the fault coverage for all mentioned four types of TDFs. [ABSTRACT FROM AUTHOR]

We propose a new methodology for Built-In Self-Test (BIST) where contrary to the traditional scan-path based Logic BIST, the proposed solution for test generation does not need any additional hardware, and will not have any impact on the working performance of the system. A class of digital systems organized as pipe-lined signal processing architectures is targeted. The on-line generated signal data used for processing in the system serve as test pattern sources. Testing under normal working conditions and with typically processed data, allows exercising of the system on-line and at-speed, facilitating the detection of dynamic faults like delays and cross-talks to achieve high test quality. The proposed new self-test method is free from the negative aspect of over-testing, compared to the traditional Logic BIST approaches, and uses minimal amount of added hardware. Experimental research was based on the case study of specialized bio-signal processor architecture. The experiments showed promising results in reducing the cost of testing and achieving high fault coverage. [ABSTRACT FROM AUTHOR]

A method is proposed for probabilistic testability analysis of digital circuits focusing on calculating the probabilistic controllability measures in terms of signal probabilities with the goal of assessment of pseudorandom test quality in digital circuits. The structure of the circuit is modeled as a macro-level network, where macros denote Fan-out-Free Regions (FFRs) of the circuit, which are represented as Structurally Synthesized BDDs (SSBDDs). SSBDD based representation allows signal probability calculation with higher speed and accuracy than using gate-level calculation approach. The proposed method is based on tracing true paths in SSBDDs, which avoids errors caused by signals' correlation and possible redundancy in the circuit, that is not possible in gate-by-gate probability calculation. A method is proposed for proving redundancy of faults, which is an extension of the same idea of SSBDD path tracing used for probability calculation. Experimental results show higher accuracy and considerable speed-up of probabilistic analysis using the proposed new macro-level approach, compared to gate-level calculation. [ABSTRACT FROM AUTHOR]

‐ A study of challenges posed by the intersection of functional and non-functional verification of hardware designs. ‐ A taxonomy for multidimensional hardware verification aspects. ‐ A state-of-the-art survey of related research works and trends enabling the multidimensional verification concept. ‐ An initial approach to perform multidimensional verification based on machine learning techniques. Advancements in electronic systems' design have a notable impact on design verification technologies. The recent paradigms of Internet-of-Things (IoT) and Cyber-Physical Systems (CPS) assume devices immersed in physical environments, significantly constrained in resources and expected to provide levels of security, privacy, reliability, performance and low-power features. In recent years, numerous extra-functional aspects of electronic systems were brought to the front and imply verification of hardware design models in multidimensional space along with the functional concerns of the target system. However, different from the software domain such a holistic approach remains underdeveloped. The contributions of this paper are a taxonomy for multidimensional hardware verification aspects, a state-of-the-art survey of related research works and trends enabling the multidimensional verification concept. Further, an initial approach to perform multidimensional verification based on machine learning techniques is evaluated. The importance and challenge of performing multidimensional verification is illustrated by an example case study. [ABSTRACT FROM AUTHOR]

The aim of the study was to analyze the relationship between resting state electroencephalographic (EEG) alpha functional connectivity (FC) and small-world organization. For that purpose, Pearson correlation was calculated between FC and small-worldness (SW). Three undirected FC measures were used: magnitude-squared coherence (MSC), imaginary part of coherency (ICOH), and synchronization likelihood (SL). As a result, statistically significant negative correlation occurred between FC and SW for all three FC measures. Small-worldness of MSC and SL were mostly above 1, but lower than 1 for ICOH, suggesting that functional EEG networks did not have small-world properties. Based on the results of the current study, we suggest that decreased alpha small-world organization is compensated with increased connectivity of alpha oscillations in a healthy brain., (Copyright © 2020 Päeske, Hinrikus, Lass, Raik and Bachmann.)

The aim of the study is to clarify the impact of the strong cyclic signal component on the results of surrogate data method in the case of resting electroencephalographic (EEG) signals. In addition, the impact of segment length is analyzed. Different non-linear measures (fractality, complexity, etc.) of neural signals have been demonstrated to be useful to infer the non-linearity of brain functioning from EEG. The surrogate data method is often applied to test whether or not the non-linear structure can be captured from the data. In addition, a growing number of studies are using surrogate data method to determine the statistical threshold of connectivity values in network analysis. Current study focuses on the conventional segmentation of EEG signals, which could lead to false results of surrogate data method. More specifically, the necessity to use end-matched segments that contain an integer number of dominant frequency periods is studied. EEG recordings from 80 healthy volunteers during eyes-closed resting state were analyzed using multivariate surrogate data method. The artificial surrogate data were generated by shuffling the phase spectra of original signals. The null hypothesis that time series were generated by a linear process was rejected by statistically comparing the non-linear statistics calculated for original and surrogate data sets. Five discriminating statistics were used as non-linear estimators: Higuchi fractal dimension (HFD), Katz fractal dimension (KFD), Lempel-Ziv complexity (LZC), sample entropy (SampEn) and synchronization likelihood (SL). The results indicate that the number of segments evaluated as non-linear differs in the case of various non-linear measures and changes with the segment length. The main conclusion is that the dependence on the deviation of the segment length from full periods of dominant EEG frequency has non-monotonic character and causes misleading results in the evaluation of non-linearity. Therefore, in the case of the signals with non-monotonic spectrum and strong dominant frequency, the correct use of surrogate data method requires the signal length comprising of full periods of the spectrum dominant frequency. The study is important to understand the influence of incorrect selection of EEG signal segment length for surrogate data method to estimate non-linearity.