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The electronics industry is present nowadays in the most various applications. A new type of technology for integrated circuits named BCD has started to be developed and appeared from the mid 1980’s. This new technology allows integrating bipolar transistors, high voltage MOS transistors named DMOS and standard CMOS technologies on one substrate. This new technology used in integrated circuits is called Smart Power (Power & Intelligence). Before that, power integrated circuits were developed only with bipolar technologies. These technologies are perfectly suitable for analogue functions such as audio amplification or charge commutation, but are not dedicated to the integration of logical functions. The motor control industry has demanded more and more solutions for smart management of motors. Those solutions are used for power window lifts where the circuit receives commands through LIN bus present in automobiles and is able to manage the motor autonomously. This type of applications requires more and more digital functions within the circuit. Without the integration of CMOS technologies, the targets of costs and performances can be achieved only using many integrated circuits. This induces issues of reliability, electromagnetic compatibility and space. This is why the family of circuits called Smart Power combining power components as well as logical functions is unavoidable in that field. The most important problem of Smart‐Power circuits is the perturbations induced by power components within the circuit itself. Those parasitic effects can affect and disturb highly the functionality of the integrated circuit and can even destroy the circuit or its main functionalities. Nowadays, it is very difficult, even hardly possible to predict the noise within the circuit substrate using the same modeling techniques as the ones used for transistor modeling. This work presents a new modeling strategy based on equivalent schematic interconnecting simple modeling elements. The particularity of the proposed elements is that the two types of charge carriers are taken into account when interconnecting these elements. The correct physical modeling of these charge transport phenomenon taking place in the substrate is then guaranteed. The advantages of this modeling technique for an integrated circuit designer are its simplicity to be implemented as well as a very short calculation time. The developed method has been used to model parasitic effects present in an industrial circuit. The results obtained are compared to current calculation method, as well as to measurements.

Metal-oxide semiconductor (MOS) field-effect transistor (FET) scaling is following the prediction of the Moore's law for the past 45 years, a key factor that enabled the IC industry to cope with the everlasting demand for higher performances. However, this scaling process becomes increasingly difficult as several limits from both process and device capabilities pop up as the technology node reaches 28nm and beyond. To stand the pace of downscaling, non-classical devices are currently introduced in the roadmap. In this context, the junctionless FET is part of these attempts. It is a new emerging device that can potentially withstand the downscaling of CMOS technology as it still has an excellent control from the gate, a low leakage current, an expected enhancement in carrier transport, besides easier fabrication processes. This dissertation focuses on the physics and modeling of nanoscale junctionless double-gate MOSFET and junctionless nanowire FETs. The first part of the thesis is focusing on junctionless transistors by discussing the advantages and limitations of such technology. A brief overview of existing models and the current status of symmetrical/asymmetrical operation of junctionless FETs in a planar double-gate configuration as well as junctionless nanowires topologies will be presented. Next, the model that is developed in this thesis is detailed in different chapter, each of which will cover a specific aspect. The model relies on Poisson-Boltzmann equation and on the drift-diffusion transport to derive charges and current in long-channel devices. It is based on two set of relationships to cover all the operating regions: from depletion to accumulation; from linear to saturation with no fitting parameter. Following a core analysis, more features are developed and added to the ideal long-channel concept. This includes modeling short-channel effects and DIBL, modeling full trans-capacitance matrix for AC simulations, modeling thermal noise and induced gate noise, modeling the inversion layer to predict off-state currents. Importantly, we have shown that equivalent symmetric devices could also be used to simulate asymmetric operation, which are likely to be the most common situation. In addition, the charge-based approach developed along the thesis has also been generalized to the quite popular junctionless nanowire architecture. Regarding junctionless FETs, technological parameter are very critical. For instance, the device cannot be made of any dimension and doping otherwise it cannot be effectively switched off at a given current. Therefore, we also derived rules providing a design-space tool with explicit links between silicon thickness and doping ensuring safe operation. Finally, since the mobility extraction in junctionless FETs is still an issue, we have developed a new method for a reliable measurement of free carriers mobility in real devices which does not assume any predefined mobility law. Based on these developments, the EPFL-JL-model was implemented into Hspice platforms to be used by circuit designers.