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A low power and high data rate wireless optical link for implantable data transmission is presented in this paper. In some neural prosthetic applications particularly in regard to neural recording system, there is a demand for high speed communication between an implanted device and an external device. An optical transcutaneous link is a promising implantable telemetry solution, since it shows lower power requirements than RF telemetry. In this paper, this advantage is further enhanced by using a modified on-off keying and a simple custom designed low power VCSEL driver. This transmitter achieves an optical transcutaneous link capable of transmitting data at 50 Mbps through the 4 mm tissue, with a tolerance of 2 mm misalignment and a BER of less than 10(-5), while the power consumption is only 4.1 mW or less.

This paper describes how to employ distributed clock gating to achieve an overall low power design of a programmable waveform generator intended for a neural stimulator. The power efficiency is enabled using global timing control combined with local amplitude distribution over a bus to the local stimulator frontends. This allows the combination of local and global clock gating for complete sub-blocks of the design. A counter and a shifter employed at the local digital stimulator reduce the design complexity for the waveform generation and thus the overall power consumptions. The average power results indicate that 63% power can be saved for the global stimulator control unit and 89-96% power can be saved for the local digital stimulator by using the proposed approach. The circuit has been implemented and successfully tested in a 0.35 µm AMS HVCMOS technology.

Miniaturization of implantable devices while drastically increasing the number of stimulation channels is one of the greatest challenges in implant manufacturing because a small but hermetic package is needed that provides reliable protection for the electronics over decades. Retinal vision prostheses are the best example for it. This paper presents a miniaturized 232-channel vision prosthesis, summarizing the studies on the individual technologies that were developed, improved and combined to fabricate a telemetrically powered retinal device sample. The implantable unit, which is made out of a high temperature co-fired alumina ceramic package containing hermetic feedthroughs, electronic circuitry and a radio frequency coil for powering is manufactured through a modified screen-printing/lasering process. The package is sealed with solder glass to provide unaffected inductive coupling to the telemetric transmitter. A 0.05 cc inner volume allows helium leak testing and mathematical lifetime estimations for moisture-induced failure of up to 100 years. The feedthroughs contact a thin-film polyimide electrode array that utilizes DLC and SiC coatings for improved interlayer adhesion of the metallic tracks to the polymer carrier. Two metal layers allow integrated wiring of the electrode array within the very limited space.

In this paper, an evaluation study of compressed sensing (CS) for neural action potential (spike) signals in MATLAB is presented. State-of-the-art neural recorders use 100 or more parallel channels to measure neural activity resulting in a data rate of 16 - 20 Mbit/s. Since a low-power design is required for an implanted neural recorder, it seems advantageous to compress the neural data prior to the wireless transmission. The continuous neural spike signals are compressed and transmitted to facilitate the possibility of an unrestricted data analysis at the receiver. Synthesized and recorded neural data sets are used to test the performance of CS. The 6-level Daubechies-8 wavelet decomposition matrix and two learned dictionary matrices are utilized as dictionaries for CS. The compression results are evaluated with the spike sorting program OSort. CS is shown to work for the compression of low-noise synthesized neural spike signals with a compression rate of 2.05, but cannot be recommended for the compression of neural spike signals in general.

A major drawback of a current-controlled stimulation is its power efficiency. However, it is commonly used in implantable stimulators due to its safety. The power efficiency of a current-controlled stimulation can be improved by reducing the headroom voltage needed in the current driver. A promising technique is to bias the transistor in triode region whereas improving output impedance through the regulated cascode structure. This comes with a feature of implicit compliance monitor which is used for the supply voltage adaptation. This paper presents an overview on recent power efficient high voltage-compliance output drivers.

This paper describes the architecture and protocol of a digital stimulator which is intended to realize a highly flexible stimulation waveform pattern. The flexibility is provided by programmable stimulation profiles such as pulse duration, frequency, polarity, amplitude level, arbitrary wave shape, train of pulses and different types of wave patterns among stimulation sites. The programmable stimulation data is therefore divided into two parts, global and local stimulation data. The global data which defines the timing of pulse duration and wave shaping, are sent sequentially to all stimulation sites using 5-bit control commands. Local stimulation data defines the initial amplitude setting and is stored at each active stimulation cell. At each stimulation site, the amplitude level can be changed during the stimulation process and consequently it generates an arbitrary wave shape. Without the need of a large memory size, the proposed simple design architecture generates not only arbitrary stimulation waveforms, but also trains of pulses as well as different types of stimulation patterns among stimulation sites are enabled.

Charge balancing is a major concern in functional electrical stimulation, since any excess charge accumulation over time leads to electrolysis with electrode dissolution and tissue destruction. Its major function is to ensure that the mean value of electrode voltage is kept within a safe level. However, it serves as a failure protection as well. This paper presents an overview on recent advances in this field, both passive and active (closed-loop) charge balancing techniques.