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During recent years, reversible logic received important attention in cryptography, optical processing, quantum computing, and nanotechnology. Among the reversible computation units, the adder unit is considered the most fundamental computation unit to build a quantum computing system. Due to its low latency, the reversible carry-lookahead adder is mostly used and considered. Parity preserving is also one of the oldest methods for error recognition in digital systems. In this article, we offer new proposals for the nanometric parity-preserving reversible 2-bit carry-lookahead adder. Compared with previous designs, we will demonstrate that our designs would be optimal in the number of garbage outputs, constant inputs, and quantum costs. In order to design circuits at a higher level, we also offer new proposals for the nanometric parity-preserving reversible 4-bit carry-lookahead adder. Since previous proposals that were presented as 4-bit did not have the reversible parity-preserving property, we proceeded with our research. [ABSTRACT FROM AUTHOR]

In this paper, we present a double-operating-mode adder which may be employed either in low-power (LP) or high-performance (HP) operating mode. The adder has a hybrid structure based on a c arry- l ookahead and c arry- p ropagate structures and hence is called CL-CPA. The selection between the two operating modes is performed through a mode selection bit during the operational period. The hybrid structure of the adder provides the feature of selecting the operating mode depending on the application deadlines and system available energy resources. The adder structure is realized by modifying the carry look-ahead tree (CLT) structure and then combining it with a carry propagate adder (CPA). During the LP mode, only the CPA structure is utilized while the CLT is deactivated through the power gating scheme. On the other hand, during the HP mode, the CLT structure is activated and the adder performs with its highest speed and power consumption using both CLT and CPA structures. The efficacy of the proposed hybrid adder is assessed by comparing its speed, power, energy, and area parameters with those of the other conventional adders obtained using HSPICE simulations for a 45-nm CMOS technology in a wide range of supply voltages. The results revel switching from the LP to HP operating mode leads to about 5.4X decrease, 2.5X increase, and 2.1X decrease in the delay, power, and energy of the 64-bit CL-CPA, respectively, averaged over the supply voltages. Also, the proposed hybrid adder provides flexibility on speed and power with an acceptable area usage for applications where both high speed and low power adders are required. [ABSTRACT FROM AUTHOR]

Currently, the demand for reliable and high performance computing is increasing due to the enlarging susceptibility of computing circuits to different environmental effects, and the advent of diverse computation-based applications. Arithmetic operators, as the main building blocks of the processing units in computing systems, are exposed to different types of single or multiple errors incurred by different faults which can seriously damage the whole system. In this paper, a new approach is presented to achieve fault-tolerant carry look-ahead adder architectures, much more efficient than the conventional methods, with the characteristic of robustness against multiple simultaneous errors. The proposed method is based on revising the carry generation block to achieve multiple error correction capability, and utilizing a modified parity prediction-based method that in combination with the proposed error correction scheme leads to multiple error detection capability. Verified by simulations, analytical assessments show that, as well as correcting or detecting all single permanent or transient errors, multiple simultaneous errors in the new carry look-ahead adders are corrected or at least detected with a high probability independent of the number of errors. Apart from having more reliability against multiple errors, these adders require lower area overheads compared to the state of the art designs as well as conventional fault-tolerant methods. [ABSTRACT FROM AUTHOR]

This paper shows that a conventional semi-custom design-flow based on a energy efficient adiabatic logic (EEAL) cell library allows any VLSI designer to design and verify complex adiabatic arithmetic units in a simple way, thus, enjoying the energy reduction benefits of adiabatic logic. A family of semi-custom EEAL-based 32-bit carry-lookahead adder (CLA) has been designed in a TSMC 90-nm CMOS process technology and verified by CADENCE Design suite. Differential cascode voltage swing (DCVS) logic has been used to implement the newly proposed EEAL and it uses only a sinusoidal clock supply to ensure correct operation. Post-layout simulations show that semi-custom adiabatic arithmetic units can save significant amount of energy, as compared to the previously reported single clocked adiabatic logic and logically equivalent static CMOS implementation. Extensive CADENCE simulations have been done for the verification of the functionality of the proposed logic structure. [ABSTRACT FROM AUTHOR]

An energy efficient adder design based on a hybrid carry computation is proposed. Addition takes place by considering the carry as propagating forwards from the LSB and backwards from the MSB. The incidence at a midpoint significantly accelerates the addition. This acceleration together with combining low-cost ripple-carry and carry-chain circuits, yields energy efficiency compared to other adder architectures. The optimal midpoint is analytically formulated and its closed-form expression is derived. To avoid the quadratic RC delay growth in a long carry chain, it is optimally repeated. The adder is enhanced in a tree-like structure for further acceleration. 32, 64 and 128-bit adders targeting 500 MHz and 1 GHz clock frequencies were designed in 65 nm technology. They consumed 11–18% less energy compared to adders generated by state-of-the-art EDA synthesis tool. [ABSTRACT FROM AUTHOR]