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Quantum Dot Cellular Automata (QCA) and reversible logic have emerged as promising alternatives to conventional CMOS technology, offering several advantages, such as ultra-dense structures and ultra-low-power consumption. Among the crucial components of processors, the Arithmetic Logic Unit (ALU) has witnessed significant advancements in reversible computing, leading to energy-efficient and high-speed computing systems, particularly beneficial for Digital Signal Processing (DSP) applications. Conventional ALUs, reliant on irreversible logic, encounter energy inefficiencies due to information loss during computations, resulting in increased power consumption. Moreover, they may face limitations in processing speed, impacting real-time processing capabilities, especially for complex DSP tasks involving intensive arithmetic and logic operations. In response to these challenges, a research paper presents a pioneering approach, proposing a novel reversible ALU design using QCA nanotechnology. The proposed design ingeniously incorporates Modified Fredkin (MF) gates, and a coplanar reversible full adder based on the HNG gate, skillfully leveraging the unique features of QCA nanotechnology to optimize the ALU's energy-efficient and high-speed performance for DSP applications. This revolutionary QCA reversible ALU comprises 330 QCA cells arranged in a compact 0.41 μm2 area, skillfully realized through the coplanar clock-zone-based crossover approach. Its core computational elements, the three MF gates, and the innovative coplanar reversible full adder empower the ALU to execute a remarkable array of 20 distinct arithmetic and logic operations, showcasing its versatility in handling diverse DSP tasks. The proposed structure undergoes extensive simulations utilizing QCADesigner version 2.0.3 to confirm its performance. The evaluation results manifest substantial improvements compared to previous designs, boasting a 30% reduction in area occupancy, a 20% decrement in cell count, a 10% reduction in latency, and a 10% decrease in quantum cost compared to the best-known previous structure. These compelling outcomes solidify the potential of the proposed reversible ALU as a transformative advancement in energy-efficient and high-speed computing for DSP applications. [ABSTRACT FROM AUTHOR]

With the rapid development of human society and the surge of engineering construction, the disturbance of the geological environment has grown substantial. The influence of extreme climatic factors and the frequency of geological disasters have increased. Landslide is an important geological disaster. The foundational research in geological disaster detection or monitoring involves studying the physical phenomena associated with the occurrence of landslides, analyzing their signal characteristics, and indirectly determining their development and changes. This scientific area is worthy of in-depth exploration. However, research on the key design and specific implementation of electromagnetic instruments tailored for landslide detection remains lacking. This study is based on the interdisciplinary theoretical system of electronic circuits, embedded computer science, digital signal processing technology, geophysics, and engineering geology. It independently develops a functional prototype of an electromagnetic detector for landslide detection. This design combines the current level of development of electronic disciplines and applies the embedded multicore Da Vinci industrial-grade computer system in the field of earth detection instruments. This study then designs and implements a landslide detection system with independent intellectual property rights. [ABSTRACT FROM AUTHOR]

In this paper, a proposal is made for a cryptographic algorithm designed for passive ultra-high-frequency (UHF) radio frequency identification systems. The algorithm relies on the advanced encryption standard (AES) as its fundamental encryption technique, augmented by two supplementary steps: the initial step involves generating a random key and the second is the randomization of data, this introduces an extra level of security to encryption process against attacks. The developed architecture has been optimized to minimize hardware resource consumption with faster execution speed. The algorithm has been simulated, synthesized and implemented in an xtreme digital signal processing (DSP) starter kit equipped with xilinx’s spartan-3A DSP 1800A edition and it serves the purpose of encrypting and decrypting user data on a radio frequency identification (RFID) passive tag. The main objective is to make it difficult to break the algorithm because of its multiple steps. The experimental results showed that the speed, functionality and cost of encryption and decryption make this a perfectly practical solution, providing a satisfactory level of security for today’s communications systems, or other electronic data transfer processes where security is required. [ABSTRACT FROM AUTHOR]

Quantum Key Distribution (QKD) has garnered significant attention due to its unconditional security based on the fundamental principles of quantum mechanics. While QKD has been demonstrated by various groups and commercial QKD products are available, the development of a fully chip-based QKD system, aimed at reducing costs, size, and power consumption, remains a significant technological challenge. Most researchers focus on the optical aspects, leaving the integration of the electronic components largely unexplored. In this paper, we present the design of a fully integrated electrical control chip for QKD applications. The chip, fabricated using 28 nm CMOS technology, comprises five main modules: an ARM processor for digital signal processing, delay cells for timing synchronization, ADC for sampling analog signals from monitors, OPAMP for signal amplification, and DAC for generating the required voltage for phase or intensity modulators. According to the simulations, the minimum delay is 11ps, the open-loop gain of the operational amplifier is 86.2 dB, the sampling rate of the ADC reaches 50 MHz, and the DAC achieves a high rate of 100 MHz. To the best of our knowledge, this marks the first design and evaluation of a fully integrated driver chip for QKD, holding the potential to significantly enhance QKD system performance. Thus, we believe our work could inspire future investigations toward the development of more efficient and reliable QKD systems. [ABSTRACT FROM AUTHOR]

Digital Signal Processing (DSP) finds a wide range of applications in various fields, including telecommunications, audio and video processing, biomedical engineering, radar systems, and image processing. Previous DSP designs faced limitations in available processing power and computational resources. Insufficient processing power could result in slower execution times, an inability to handle complex algorithms, or limited capacity to process high-speed or large-scale signals. As the demand for minimal power consumption in DSP circuits continues to grow, reversible logic and quantum-dot cellular automata (QCA) have emerged as promising technologies due to their inherent ability to reduce energy loss. Within this landscape, the arithmetic and logic unit (ALU) plays a vital role in complex circuitry, serving as a key component in digital signal processing applications. However, challenges persist, including high quantum cost and the need to limit the number of cells in the ALU design. To address these challenges, our research aims to develop an efficient ALU by integrating reversible logic and QCA technology. Our focus will be on generating essential components, such as Feynman gates, Fredkin gates, and full adder circuits, which serve as foundational building blocks for reversible logic and QCA designs. These components will be combined to construct a comprehensive ALU capable of performing 20 different operations. Our implementation efforts will be centered around QCADesigner, with a specific emphasis on digital signal processing systems that prioritize energy efficiency and optimal utilization of occupied areas. [ABSTRACT FROM AUTHOR]

This paper proposes an efficient design of Hamming (11, 7) encoder utilising Full Swing-Gate Diffusion Input (FS-GDI) approach in 65 nm technology nano-size node. The proposed design of Hamming codes aims to improve the power and area efficiency through reducing of transistors count by employing power-efficient logic style. Encoding circuits of Hamming code (11, 7) and (7, 4) are designed using the various traditional and proposed approaches. The amount of consumed power, delay time, Power Delay Product (PDP) and hardware simplicity are employed as a metrics for evaluating the efficiency of the proposed designs of encoding circuits. The simulation experiments are executed utilising Cadence Virtuoso simulator package. These experiments revealed that the proposed designs of Hamming encoding circuits achieve delay time reduction by 50.91% and 20% for Hamming codes (7, 4) and (11, 7), respectively. Also, hardware (H/W) simplicity and area efficiency of the circuits are improved by 50% compared to CMOS-based circuits. From the results analysis, the proposed FS-GDI based Hamming encoding circuits achieve efficient power and delay optimising. Hence, the power consumption, delay and area in communications systems and DSP circuits due to encoding process are reduced. The whole performance of DSP circuits can be more power/area efficient. [ABSTRACT FROM AUTHOR]

Approximate computing is an emerging paradigm that can tolerate some loss of accuracy to improve the energy consumption and design complexity. Multiplication is one of the important computational components in various digital signal processing (DSP) applications. Improvement of multipliers, as the building blocks of an approximate computing systems, has received significant attention. Compressors are key elements in an approximate multiplier to have an optimal design with high performance. This paper proposes an approximate/exact 4–2 compressor and an exact 5–2 compressor in carbon nanotube field-effect transistors (CNTFET) technology for utilisation in an approximate multiplier. Four efficient designs for utilising the proposed compressors are introduced and analysed for a Wallace multiplier. All of the proposed circuits are analysed in 32 nm CNTFET Stanford technology and are simulated by HSPICE. In addition, as an image processing application of approximate multipliers, this paper compares the quality metrics of the image multiplication for the proposed designs and previously presented approximated multipliers. For example, the proposed schemes provide excellent results in structural similarity index up to 99%, and peak signal-to-noise ratio more than 45 dB. Also, it uses figure of metric (FOM) that includes the accuracy and quality metrics of the approximate multipliers. The simulation results demonstrate the efficiency of proposed designs. [ABSTRACT FROM AUTHOR]

In the modern technological era of sophisticated applications and high-quality communications, a platform of clever strategy and quickly updated systems is needed. It should be capable of withstanding the fastest emerging problems like signal attenuation and hostile actions intended to harm the whole network. The main contributions of this work are the production of an OFDM system (with low cost) that can sustain high-speed communications and be easily adjusted with new integrated code while exhibiting the feasibility of implementing a transmitter–receiver system in the same DSP and demonstrating the holistic approach with the qualitative integration of such an architecture in a warfare scenario. Specifically, in this research, the point of view is toward three facts. The first is to show a method of quick self-checking the operational status of a digital signal processor (DSP) platform and then the pedagogical issues of how to fast check and implement an updated code inside DSPs through simple schematics. The second point is to present the prototype system that can easily be programmed using a graphical user interface (GUI) and can change its properties (such as the transmitted modulated sinusoids—orthogonal frequency division multiplexing subcarriers). Alongside the presentation, the measurements are presented and discussed. These were acquired with the use of an oscilloscope and spectrum analyzer. The third point is to qualitatively show the application of such a system inside a modern warfare environment and to recommend various potential system responses according to the development of such a platform of reconfigurable implemented OFDM systems. The implementation was performed for two types of systems: (1) transmitter and (2) transmitter–receiver system. Notably, the system acts quickly with a delay of about 1 msec in the case of transmitting and receiving in the same DSP, suggesting excellent future results under real conditions. [ABSTRACT FROM AUTHOR]

The advantageous applications of magnetic bistable microwires have emerged during long-lasting research. They have a wide range of applications in the scientific sphere or technical practice. They can be used for various applications, including magnetic memories, biomedicine, and sensors. This manuscript is focused on the last-mentioned application of microwires—sensors—discussing various digital signal processing techniques used in practical applications. Thanks to the highly sensitive properties of microwires and their two stable states of magnetization, it is possible to perform precise measurements with less demanding digital processing. The manuscript presents four practical signal-processing methods of microwire response using three different experiments. These experiments are focused on detecting the signal in a simple environment without an external magnetic background, measuring with the external background of a ferromagnetic core, and measuring in harsh conditions with a strong magnetic background. The experiments aim to propose the best method under various conditions, emphasizing the quality and signal processing speed of the microwire signal. [ABSTRACT FROM AUTHOR]

Due to their user-friendliness and reliability, biometric systems have taken a central role in everyday digital identity management for all kinds of private, financial and governmental applications with increasing security requirements. A central security aspect of unsupervised biometric authentication systems is the presentation attack detection (PAD) mechanism, which defines the robustness to fake or altered biometric features. Artifacts like photos, artificial fingers, face masks and fake iris contact lenses are a general security threat for all biometric modalities. The Biometric Evaluation Center of the Institute of Safety and Security Research (ISF) at the University of Applied Sciences Bonn-Rhein-Sieg has specialized in the development of a near-infrared (NIR)-based contact-less detection technology that can distinguish between human skin and most artifact materials. This technology is highly adaptable and has already been successfully integrated into fingerprint scanners, face recognition devices and hand vein scanners. In this work, we introduce a cutting-edge, miniaturized near-infrared presentation attack detection (NIR-PAD) device. It includes an innovative signal processing chain and an integrated distance measurement feature to boost both reliability and resilience. We detail the device's modular configuration and conceptual decisions, highlighting its suitability as a versatile platform for sensor fusion and seamless integration into future biometric systems. This paper elucidates the technological foundations and conceptual framework of the NIR-PAD reference platform, alongside an exploration of its potential applications and prospective enhancements. [ABSTRACT FROM AUTHOR]

In signal processing applications, the multipliers are essential component of arithmetic functional units in many applications, like digital signal processors, image/video processing, Machine Learning, Cryptography and Arithmetic & Logical units (ALU). In recent years, Profuse multipliers are there. In that, Vedic multiplier is one of the high-performance multiplications and it is used to signal/image processing applications. In order to ameliorate the performance of this multiplier further, by proposed a novel multiplier using hybrid compressor. The proposed hybrid compressor-based multiplier is designed and implemented in Field programmable Gate Array (FPGA—spartan 6). The synthesis result shows that the speed of proposed hybrid compressor-based multiplier gets improved as compared to Array multiplier (35.83%), Wallace tree multiplier (34.58%), Vedic Multiplier based on Carry look ahead adder (CLA) (28.49%), Vedic Multiplier based on Ripple carry adder (RCA) (20.65%), Booth Multiplication (21.65%) and Vedic Multiplication based on Han-Carlson Adder (HCA) (20.10%) and Hybrid multiplier using Carry Select Adder (CSELA) (17.81%) and Hybrid Vedic Multiplier (7.15%). [ABSTRACT FROM AUTHOR]

Emotion recognition systems from speech signals are realized with the help of acoustic or spectral features. Acoustic analysis is the extraction of digital features from speech files using digital signal processing methods. Another method is the analysis of time-frequency images of speech using image processing. The size of the features obtained by acoustic analysis is in the thousands. Therefore, classification complexity increases and causes variation in classification accuracy. In feature selection, features unrelated to emotions are extracted from the feature space and are expected to contribute to the classifier performance. Traditional feature selection methods are mostly based on statistical analysis. Another feature selection method is the use of metaheuristic algorithms to detect and remove irrelevant features from the feature set. In this study, we compare the performance of metaheuristic feature selection algorithms for speech emotion recognition. For this purpose, a comparative analysis was performed on four different datasets, eight metaheuristics and three different classifiers. The results of the analysis show that the classification accuracy increases when the feature size is reduced. For all datasets, the highest accuracy was achieved with the support vector machine. The highest accuracy for the EMO-DB, EMOVA, eNTERFACE'05 and SAVEE datasets is 88.1%, 73.8%, 73.3% and 75.7%, respectively. [ABSTRACT FROM AUTHOR]

Blind source separation (BSS), as a digital signal processing approach, focuses on estimating the underlying source signals from their linear mixtures without any prior information about the source signals and mixing matrix. Conventional methods for the BSS, however, are incapable of separating the complex-valued source signals. By leveraging the negative conjugate gradient to minimize the least mean square error reconstruction (LMSER) principle in complex domain, this paper proposes a collection of least-squares algorithms for complex-valued BSS (CBSS), including least-mean square (LMS)-type algorithms and recursive least-squares (RLS)-type algorithms. We demonstrate the availability of the proposed algorithms in both circular and non-circular source signals separation. Especially, the RLS algorithm for the CBSS without prewhitening is superior in cross-talking criterion to the others, as verified by computer simulations on artificial source signals. [ABSTRACT FROM AUTHOR]

In this study, it was aimed to find out whether electroencephalographic (EEG) frequency bands can be used to distinguish people with obstructive sleep apnea (OSA) from those who do not have it. 11842 different cases taken from 121 patients suffering from OSA were combined with the case study of 30-person control group without sleep apnea. Apneas were highlighted at the respiration-record channels and EEG records which are concurrent with abnormal respiration cases were extracted from C4-A1 and C3-A2. Following that, they were examined with Fourier and Wavelet Transforms using a new software that was developed by us. The percentage values of Delta (0, 5-4 Hz), Theta (4-8 Hz), Alpha (8-13 Hz) and Beta (13-30 Hz) frequency bands were evaluated with the help of t-test and ROC Analysis to differentiate between apneas. The C3-A2 Beta (%) frequency level gave the highest distinguishing asset (AUC=0.662; p<0.001); however, the C3-A2 Alpha (%) level yielded the lowest distinguishing (AUC=0.536; p<0.001). Similarly, the C4-A1 Alpha (%) level produced the lowest distinguishing asset (AUC=0.536; p<0.001) whereas the C4-A1 Beta (%) frequency level gave the highest distinguishing asset (AUC=0.658; p<0.001). The chief finding of this study suggests that the EEG rates of patients with OSA differ from those of patients without OSA and following the changes at these channels may give rise to detection of apneas, and the Beta (%) yielded the most meaningful result among four different frequency bands in the study. [ABSTRACT FROM AUTHOR]

This paper investigates optimizing the power exchange between electric vehicles (EVs) and the grid, with a specific focus on the DC-DC converters utilized in vehicle-to-grid (V2G) systems. It specifically explores using model predictive control (MPC) in synchronous boost converters to enhance efficiency and performance. Through experiments and simulations, this paper shows that replacing diodes with SIC MOSFETs in boost converters significantly improves efficiency, particularly in synchronous mode, by minimizing the deadtime of SIC MOSFETs during switching. Additionally, this study evaluates MPC's effectiveness in controlling boost converters, highlighting its advantages over traditional control methods. Real-world validations further validate the robustness and applicability of MPC in V2G systems. This study utilizes TMS320F28379D, one of Texas Instruments' leading digital signal processors, enabling the implementation of MPC with a high PWM frequency of up to 200 MHz. This processor features dual 32-bit CPUs and a 16-bit ADC, allowing for high-resolution readings from sensors. Leveraging digital signal processing technologies and advanced electronic circuits, this study advances the development of high-performance boost converters, achieving power outputs of up to 48 watts and output voltages of 24 volts. Electronic circuits (PCB boards) have been devised, implemented, and evaluated to showcase their significance in advancing efficient V2G integration. [ABSTRACT FROM AUTHOR]

In recent years, headphones have become increasingly popular worldwide. There are numerous models on the market today, varying in technical characteristics and offering different listening experiences. This article presents an application for simulating the sound response of specific headphone models by physically wearing others. In the future, for example, this application could help to guide people who already own a pair of headphones during the decision-making process of purchasing a new headphone model. However, the potential fields of application are much broader. An in-depth study of digital signal processing was carried out with the implementation of a computational model. Prior to this, an analysis was performed on impulse response measurements of specific headphones, which allowed for a better understanding of the behavior of each set of headphones. Finally, an evaluation of the entire system was conducted through a listening test. The analysis of the results showed that the software works reasonably well in replicating the target headphones. We hope that this work will stimulate further efforts in the same direction. [ABSTRACT FROM AUTHOR]

Nowadays, the application of computations and communications is needed for high performance, reduced size and lower power utilisation. The multiply and add functions are one of the frequently used operations in digital signal processing. Various types of multipliers are available in digital Various types of multipliers are available for various Signal processing applications.. Among these multipliers, Vedic multiplier is one of the most optimised multipliers used in a signal processing module. In the existing method, the Vedic multiplier is designed with conventional adders, which is having higher area utilisation, lower speed and higher power consumption. Hence, the modified Vedic multiplier is proposed to improve the speed of multiplication using hybrid technology. The partial products of the proposed multiplication are added using 2 × 2 Vedic multiplier and hybrid carry select adder (binary to excess one converter (BEC), Han-Carlson adder and Multiplexer). The critical path delays of hybrid 4 × 4 Vedic multiplier are the summation of 2 × 2 Vedic multiplier, two full adders, two multiplexers and two BECs for producing the final product. The proposed hybrid Vedic multiplier is operated at high speed with reduced size as compared to the existing multiplier techniques. The proposed hybrid Vedic multiplier is designed and simulated using Verilog HDL and implemented in Spartan 6 field-programmable gate array device. The implementation results showed that the delay of the proposed multiplier gets ameliorated as compared to array multiplication (30.84%), Wallace tree multiplication (29.52%), multiplication based on compressor (23.71%), Vedic multiplication by carry look-ahead adder (22.91%), Vedic multiplication by ripple carry adder (14.45%), revised booth multiplication (15.42%) and Vedic multiplication by Han-Carlson adder with BEC (13.95%) and hybrid multiplier (11.37%). [ABSTRACT FROM AUTHOR]

Blended learning is the latest and inevitable trend in the development of education. Although blended learning research is on the rise, fewer studies examine the learning behaviour of college students in blended learning environments. This study aimed to investigate the learning behaviours of students in the field of computer science and examine these behaviours using data mining algorithms, taking the teaching practice of the Digital Signal Processing course as a case study. A total of 18 behavioural indicators were extracted and divided into three categories: basic learning behaviours, self-regulated learning behaviours, and extended learning behaviours. Data analysis of the behavioural indicators yielded the following conclusions: (1) Students did not have the habit of watching course playback and were less receptive to multiple online learning platforms; (2) Students' midterm performance and duration of livestream watching directly affected their basic learning behaviours, with all indicators of self-regulated and extended learning behaviours showing significant correlations; (3) The clustering of learning behaviours yielded four different learner patterns, which calls for personalised teaching strategies; (4) The random forest algorithm had an accuracy of 95.4% in predicting performance of the four types of learners. [ABSTRACT FROM AUTHOR]

We report on the operation of a coherent population trapping (CPT) microcell atomic clock using a pulsed Ramsey-like interrogation. The Ramsey-CPT sequence, defined by two-step optical pulses separated by a free-evolution dark time, is produced by switching on and off the output power of a low-power vertical-cavity surface-emitting laser, through direct modulation of its driving current. High-contrast and narrow Ramsey-CPT fringes are detected without the use of any external optical modulator stage. We demonstrate closed-loop operation of the clock based on high-speed digital signal processing implemented in a field programmable gate array board. The clock's short-term fractional frequency stability is 1.3 × 10−10 τ − 1 / 2 until 2000 s. A power light-shift coefficient of 8 × 10−11/μW, in relative value, is obtained for a dark time of 150 μs. This value is about ten times lower than in the continuous regime. These results show the feasibility of fully integrated atomic clocks based on Ramsey spectroscopy, which could provide enhanced long-term stability. [ABSTRACT FROM AUTHOR]

Rapid societal development and increased engineering construction have exacerbated the disturbance of the geological environment. The impact of extreme climatic factors has grown, leading to a surge in geological disasters, with landslides emerging as particularly significant. Consequently, fundamental research in geological disaster detection or monitoring necessitates an in-depth study of the physical phenomena accompanying landslides' development, evolution, and occurrence. Exploring the signal characteristics associated with landslides is crucial to indirectly understanding their development and change processes—a scientific question deserving thorough exploration. Despite this research's importance, there is a notable gap in the investigation of the key design and specific implementation of electromagnetic instruments tailored for landslide detection. This gap is particularly pronounced in designing and implementing data acquisition software for electromagnetic instruments. This interdisciplinary research draws on theoretical frameworks from embedded computer science, software engineering, digital signal processing technology, geophysics, and engineering geology. It focuses on developing specialized data acquisition application software for landslide detection or monitoring, contributing to the scientific understanding of landslide development and providing independent intellectual property in the electromagnetic wave signal detection field. [ABSTRACT FROM AUTHOR]

The (p, fc)-parametrization technique introduced by Alaca provides an alternative approach for formulating several new Eisenstein series identities involving Borwein's theta functions. As a practical example, we have computed the convolution sum of divisor functions, which exhibit a connection with Eisenstein series. [ABSTRACT FROM AUTHOR]

This paper proposes an analytical calculation method of frequency characteristics of DC input impedances of an IPM motor drive system for design and stability analysis by the impedance method. The proposed method is based on an averaged frequency model linearized at an operating point. The developed small‐signal model considers control principles and mechanical perturbations. It is an analog and digital mixed model which is controlled by a digital signal processor system. Analysis examples of frequency characteristics for the impedance method by the proposed method are investigated and validated analytically and experimentally. [ABSTRACT FROM AUTHOR]

In this paper, a spectrally efficient silicon photonics phase‐diverse direct‐detection receiver based on asymmetric self‐coherent detection is proposed. The receiver is hardware efficient and composed of only two photodiodes and two analog‐to‐digital channels to accurately recover complex double‐sideband signals by leveraging an optimized integrated silicon racetrack resonator with near‐ideal phase responses. Moreover, the periodicity of the resonator response enables the receiver to support multi‐channel transmission such as dense wavelength‐division multiplexing. The receiver circuit is fabricated and characterized. In 40‐km transmission experiments, a record net electrical spectral efficiency of 7.10 bit s−1 Hz−1 per wavelength and per polarization is achieved, where a net 208‐Gb s−1 32QAM transmission is demonstrated using 29.3‐GHz electrical bandwidth. Furthermore, the receiver achieves net 220‐Gb s−1 16QAM transmissions in 14 channels from 1527 to 1550 nm with 205‐GHz spacing, and a maximum 240‐Gb s−1 net capacity at a single channel. Such a performance is reached with only standard coherent digital signal processing stacks including all‐linear equalization. [ABSTRACT FROM AUTHOR]

Enhanced Loran (eLoran) is the most important backup system for Global Navigation Satellite System (GNSS). However, most current eLoran demodulation methods are based on digital signal processing, which may produce large errors under the influence of strong interference or noise. The authors propose an eLoran signal message prediction algorithm based on deep learning. Using time‐frequency (TF) analysis convert one‐dimensional signal into two‐dimensional high‐resolution image. It improves Alexnet by adjusting the convolutional layer structure, adding an attention module, and reducing the pooling layer window to construct the Alexnet‐ECA network. The network is used to identify TF image features and predict signal message. The experimental results show that novel method for eLoran signal message prediction based on Alexnet‐ECA can achieve high accuracy and robustness in various SNR scenarios. The accuracy is more than 90% at SNR greater than 10db and not less than 80% even in the complex environments. Compared with Resnet34 and VGG16 networks, Alexnet‐ECA demonstrates its efficiency and effectiveness using real measurement data. This method can enhance the performance and reliability of eLoran receivers and applications. [ABSTRACT FROM AUTHOR]

This study investigates the biomechanical impact of a passive Arm-Support Exoskeleton (ASE) on workers in wool textile processing. Eight workers, equipped with surface electrodes for electromyography (EMG) recording, performed three industrial tasks, with and without the exoskeleton. All tasks were performed in an upright stance involving repetitive upper limbs actions and overhead work, each presenting different physical demands in terms of cycle duration, load handling and percentage of cycle time with shoulder flexion over 80°. The use of ASE consistently lowered muscle activity in the anterior and medial deltoid compared to the free condition (reduction in signal Root Mean Square (RMS) − 21.6 % and − 13.6 % , respectively), while no difference was found for the Erector Spinae Longissimus (ESL) muscle. All workers reported complete satisfaction with the ASE effectiveness as rated on Quebec User Evaluation of Satisfaction with Assistive Technology (QUEST), and 62% of the subjects rated the usability score as very high (>80 System Usability Scale (SUS)). The reduction in shoulder flexor muscle activity during the performance of industrial tasks is not correlated to the level of ergonomic risk involved. This preliminary study affirms the potential adoption of ASE as support for repetitive activities in wool textile processing, emphasizing its efficacy in reducing shoulder muscle activity. Positive worker acceptance and intention to use ASE supports its broader adoption as a preventive tool in the occupational sector. [ABSTRACT FROM AUTHOR]

Passive location based on TDOA (time difference of arrival) and FDOA (frequency difference of arrival) is the mainstream method for target localization. This paper proposes a fast time–frequency difference positioning method to address issues such as low accuracy, large computational resource utilization, and limited suitability for real-time signal processing in the conventional CAF (cross-ambiguity function)-based approach, aiming to complete the processing of the target radiation source to obtain the target parameters within a short timeframe. In the mixing product operation step of the CAF, a frequency-domain approach replaces the time-domain convolution operation in PW-ZFFT (pre-weighted Zoom-FFT) to reduce the computational load of the CAF. Additionally, a quadratic surface fitting method is used to enhance the accuracy of TDOA and FDOA. The localization solution is obtained using Newton's method, which can provide more accurate results compared to analytical methods. Next, a signal processing platform is designed with FPGA (field-programmable gate array) and multi-core DSP (digital signal processor), and works by dividing and mapping the algorithm functional modules according to the hardware's characteristics. We analyze the architectural advantages of multi-core DSP and design methods to improve program performance, such as EDMA transfer optimization, inline function optimization, and cache optimization. Finally, this paper constructs simulation tests in typical positioning scenarios and compares them to hardware measurement results, thus confirming the correctness and real-time capability of the program. [ABSTRACT FROM AUTHOR]

Permanent magnet (PM) motors are gaining prominence in subsea applications such as drilling, pumping, and boosting for oil and natural gas extraction. These motors are gradually replacing traditional induction motors. However, starting and operating PM motors at low speeds under heavy loads poses significant challenges. This is because of unknown initial rotor positions and resistive voltage drops due to the presence of a sinewave filter, transformer, and long cable. An unknown rotor position may result in temporary reverse speed, which may cause a loss of synchronism; therefore, initial rotor position estimation is preferable. Additionally, addressing the voltage drop issue requires careful voltage compensation to avoid transformer core saturation. In this paper, an enhanced V / H z starting of a PM motor is proposed with initial position detection (IPD) and voltage compensation to start the motor reliably with a heavy load. The proposed control method is verified with controller hardware in the loop (C-HIL) real-time simulation using a Typhoon HIL-604 emulator and a Texas Instruments TMS320F28335 digital signal processor (DSP) control card. [ABSTRACT FROM AUTHOR]

In electrified transportation systems, power system failures can lead to greater disasters. Therefore, the reliability of converters in transportation systems has been a concern. Fault-tolerant techniques are widely applied to ensure that converters can continue to supply loads under fault conditions. Fault diagnosis as a prerequisite for fault tolerance has also become a research hotspot. This paper proposes a fast method for fault diagnosis of high-frequency LLC converters. The proposed fault diagnosis method is based on the observation of the voltage across the resonant capacitor to determine and locate the faulty power switch, providing a basis for fault tolerance. This diagnosis method requires a voltage sensor, which is also necessary for some control methods. When applying these control methods, the proposed fault diagnosis method can be used without additional sensors, beneficial for cost reduction. A full-bridge LLC converter controlled by a digital signal processor was used as an experimental platform to verify the effectiveness and speed of the proposed diagnostic method. The results show that the proposed fault diagnosis method can achieve the fast diagnosis of high-frequency LLC converters in a short time and with only minimal computational resources. [ABSTRACT FROM AUTHOR]

Modern electrical power systems are characterized by a high rate of transient processes, the use of digital monitoring and control systems, and the accumulation of a large amount of technological information. The active integration of renewable energy sources contributes to reducing the inertia of power systems and changing the nature of transient processes. As a result, the effectiveness of emergency control systems decreases. Traditional emergency control systems operate based on the numerical analysis of power system dynamic models. This allows for finding the optimal set of preventive commands (solutions) in the form of disconnections of generating units, consumers, transmission lines, and other primary grid equipment. Thus, the steady-state or transient stability of a power system is provided. After the active integration of renewable sources into power systems, traditional emergency control algorithms became ineffective due to the time delay in finding the optimal set of control actions. Currently, machine learning algorithms are being developed that provide high performance and adaptability. This paper contains a meta-analysis of modern emergency control algorithms for power systems based on machine learning and synchronized phasor measurement data. It describes algorithms for determining disturbances in the power system, selecting control actions to maintain transient and steady-state stability, stability in voltage level, and limiting frequency. This study examines 53 studies piled on the development of a methodology for analyzing the stability of power systems based on ML algorithms. The analysis of the research is carried out in terms of accuracy, computational latency, and data used in training and testing. The most frequently used textual mathematical models of power systems are determined, and the most suitable ML algorithms for use in the operational control circuit of power systems in real time are determined. This paper also provides an analysis of the advantages and disadvantages of existing algorithms, as well as identifies areas for further research. [ABSTRACT FROM AUTHOR]

We describe a method for reducing the cost of optical frequency domain reflectometer (OFDR) hardware by replacing two reference channels, including an auxiliary interferometer and a gas cell, with a single channel. To extract useful information, digital signal processing methods were used: digital frequency filtering, as well as empirical mode decomposition. It is shown that the presented method helps to avoid the use of an unnecessary analog-to-digital converter and photodetector, while the OFDR trace is restored by the equal frequency resampling (EFR) algorithm without loss of high resolution and with good measurement repeatability. [ABSTRACT FROM AUTHOR]

Quantum key distribution (QKD) is one quantum technology that can provide secure encryption keys for data transmission. The secret key rate (SKR) is a core performance indicator in QKD, which directly determines the transmission rate of enciphered data. Here, for the first time, we demonstrate a high-key-rate Gaussian-modulated continuous-variable QKD (CV-QKD) using telecom optical components. The framework of CV-QKD over these components is constructed. Specifically, the high-rate low-noise Gaussian modulation of coherent states is realized by a classical optical IQ modulator. High-baud low-intensity quantum signals are received by an integrated coherent receiver under the shot-noise limit. A series of digital signal processing algorithms are proposed to achieve accurate signal recovery and key distillation. The system can yield a high asymptotic SKR of 10.37 Mbps within 20 km standard telecom fiber, and the secure distance can exceed 100 km. This result confirms the feasibility of CV-QKD with state-of-the-art performance using telecom optical components. Besides, due to the ease of integrating these discrete components, it provides a high-performance and miniaturized QKD solution for the metropolitan quantum network. [ABSTRACT FROM AUTHOR]

Solid-state transformers (SSTs) are expected to become one of the most powerful and adaptable devices that allow controllable voltage, power factor correction, fault isolation, compact size as compared to their low-frequency (50 Hz/60 Hz) counterparts. The high-frequency isolation of single-phase modified quasi-Z-source AC–AC converter (SPM-qZAC) employing bidirectional switches to create the single-stage SPM-qZAC-based SST is proposed in this paper. The proposed topology offers all the benefits of conventional impedance source topologies, including single-stage power conversion with a small footprint, buck–boost operation and retaining or reversing the phase angle. Moreover, the presented converter topology allows to share the same ground between input and output voltage, continuous input current, no input–output LC filters and performs AC–AC power conversion without the use of DC storage, making it suitable for AC voltage regulation. This study introduces two modulation schemes for SPM-qZAC-based SST. Finite control set model predictive control (FCS-MPC) which is a current control technique at variable switching frequency is employed owing to the capabilities of modern digital signal processing. Further, an adaptive hysteresis band-based delta sigma modulation (DSM) technique that offers the benefit of constant switching frequency (CSF) is proposed as an alternative voltage control-based modulation of the same topology. Various performance indices including steady-state response, total harmonic distortion of source current and dynamic response are assessed through simulation studies using MATLAB/Simulink software and real-time simulation environment using RT-Lab with OPAL-RT OP4510. It is observed that SPM-qZAC exhibits good performance when modulated using either modulation techniques; however, CSF-DSM technique offers an additional benefit of constant switching frequency. [ABSTRACT FROM AUTHOR]

A frequency/phase/amplitude estimator is arguably one of the most crucial components in the control and synchronization of grid-connected equipment. Such an estimator may also be useful for monitoring and protection purposes in power systems. In this paper, an open-loop (and therefore unconditionally stable) estimator for the accurate and rapid extraction of the grid voltage phase, frequency, and amplitude is presented. In designing the proposed technique, special focus is given to applications operating at a low sampling rate. Examples of such applications include high-power converters, where both switching and sampling frequencies are very low. The study concludes with a comprehensive evaluation of the proposed estimator, demonstrating its effectiveness in accurately and swiftly estimating the fundamental parameters of grid voltage under low sampling rates. It highlights the estimator's enhanced performance in scenarios of distorted grid conditions and its superiority in filtering capabilities compared to traditional methods. These findings underline the estimator's potential for broad applicability in power system monitoring, protection, and control. [ABSTRACT FROM AUTHOR]

A grid-tied fuel cell (FC) system demands efficient power conversion, power quality preservation, grid stability, power flow management, renewable energy source (RES) integration, and enhanced grid resilience. Achieving these goals requires a precise inverter circuit switch approach. A boost power converter connected to the FC stack ensures voltage regulation, power conditioning, efficient power transfer, system integration, control, and protection. This enhances FC system adaptability and compatibility across various applications, minimizing input current ripples for prolonged FC lifespan. This study introduces a novel DC-DC boost converter with an artificial neural network (ANN) controller to reduce FC input current ripples and enhance FC stack-generated voltage for grid applications. It also presents a space vector sinusoidal pulse width modulation (SVPWM) technique for FC-based three-phase grid-tied inverters. This offers improved voltage utilization, precise voltage and current control, reduced harmonic distortion, rapid response, flexibility, scalability, reduced total harmonic distortion (THD), and over-modulation capability. The proposed SVPWM technique utilizes a digital signal processing (DSP)-based controller, combining high-speed processing, precision, and real-time capabilities to enhance system performance and efficiency. (a) Theoretical and (b) laboratory workbench representation of the proposed neural network-based step-up converter with integration of voltage fed and SVPWM switching-based three phase inverter, connection from renewable energy sources to three-phase grid. [Display omitted] • A grid-tied fuel cell-based three-phase inverter system is presented. • A boost converter is introduced, utilizing an artificial neural network controller. • Minimizing fuel cell input current peak-to-peak ripples successfully is done. • A new space vector sinusoidal pulse width modulation technique is presented. • Topology enhances the voltage precision, and minimizes the total harmonic distortion. [ABSTRACT FROM AUTHOR]

The ability to sense propagating electromagnetic plane waves based on their directions of arrival (DOAs) is fundamental to a range of radio frequency (RF) sensing, communications, and imaging applications. This paper introduces an algorithm for the wideband true time delay digital delay Vandermonde matrix (DVM), utilizing Thiran fractional delays that are useful for realizing RF sensors having multiple look DOA support. The digital DVM algorithm leverages sparse matrix factorization to yield multiple simultaneous RF beams for low-complexity sensing applications. Consequently, the proposed algorithm offers a reduction in circuit complexity for multi-beam digital wideband beamforming systems employing Thiran fractional delays. Unlike finite impulse response filter-based approaches which are wideband but of a high filter order, the Thiran filters trade usable bandwidth in favor of low-complexity circuits. The phase and group delay responses of Thiran filters with delays of a fractional sampling period will be demonstrated. Thiran filters show favorable results for sample delay blocks with a temporal oversampling factor of three. Thiran fractional delays of orders three and four are mapped to Xilinx FPGA RF-SoC technologies for evaluation. The preliminary results of the APF-based Thiran fractional delays on FPGA can potentially be used to realize DVM factorizations using application-specific integrated circuit (ASIC) technology. [ABSTRACT FROM AUTHOR]

We are completely aware of the fact that ternary algebraic structures in some way naturally occur in diverse fields of theoretical and mathematical physics, computer science, especially in ternary operators in Java and Python, ternary logic applied for digital signal processing, and musical systems for song composition. The primary aim of this research is to examine ternary semigroups in the context of hybrid quasi-ideals and hybrid A-ideals. Different features of hybrid quasi-ideals and hybrid A-ideals in the ternary semigroup are discussed. In addition, the idea of minimal hybrid A-ideals of ternary semigroups is defined. [ABSTRACT FROM AUTHOR]

To improve the effect of immersive animation design, this paper combines digital media technology (DT) to establish an immersive animation design system and analyzes the media digital signal data processing algorithm. According to the advantages and disadvantages of the FHT algorithm and probabilistic algorithm, this paper proposes the FHT-SLM algorithm and the FHT-IPTS algorithm. Moreover, this paper analyzes the basic principle of TPWC transform and M-TPWC and the CO-OFDM system of cascaded FHT algorithm and M-TPWC algorithm. Finally, this paper simulates the CO-OFDM simulation system built by Matlab2018.a and Optisystem. Through the experimental analysis results, the reliability of the algorithm and the system in this paper is verified, and the design effect of immersive animation is effectively improved. [ABSTRACT FROM AUTHOR]

Unlike quaternions and split quaternions, reduced biquaternions satisfy the multiplication commutative rule and are commonly used in image processing, fuzzy recognition, image compression, Hopfield neural networks, and digital signal processing. However, although algebraic techniques have been developed for the diagonalisation of quaternion and split quaternion matrices, the diagonalisation of a reduced biquaternion matrix is yet to be studied. In this study, we derive sufficient and necessary conditions for the diagonalisation of a reduced biquaternion matrix and devise two numerical methods for the diagonalisation of a reduced biquaternion matrix. These methods were derived using complex and real representations in the reduced biquaternionic algebra. [ABSTRACT FROM AUTHOR]

The arithmetic and logic unit (ALU) is a key element of complex circuits and an intrinsic part of the most widely recognized complex circuits in digital signal processing. Also, recent attention has been brought to reversible logic and quantum-dot cellular automata (QCA) because of their intrinsic capacity to decrease energy dissipation, which is a crucial need for low-power digital circuits. QCA will be the preferred technology for developing the subsequent generation of digital systems. These technologies played a substantial role in the design of the ALU for operations such as multiplication, subtraction, and division. In developing reversible logic and QCA technologies, the ALU is frequently studied as a central unit. Implementing an efficient ALU with low quantum cost and a small number of cells based on an efficient reversible block can solve all previous issues. Therefore, this research constructs a Feynman gate, a Fredkin gate, and full adder circuits using reversible logic and QCA technology. Using all of the specified circuits, a 20-operation ALU is constructed. The power consumption of the proposed ALU under various energy ranges demonstrated significant improvements over earlier designs. [ABSTRACT FROM AUTHOR]

Digital signal processing (DSP) is used in computer processing to conduct different signal-processing tasks. The DSPs are used in the series numbers representing a continuous variable in a domain such as time, area, or frequency. The multiply-accumulate (MAC) unit is crucial in various DSP applications, including convolution, discrete cosine transform (DCT), Fourier Transform, etc. Thus, all DSPs contain a critical MAC unit in signal processing. The MAC unit conducts multiplication and accumulation operations for continuous and complicated DSP application processes. On the other hand, in the MAC structure, the stability of the circuit and the occupied area pose some significant challenges. However, high-performance quantum technology can easily overcome all the previous shortcomings. Hence, this paper suggests an efficient MAC for DSP applications using a Vedic multiplier, half adder, and accumulator based on quantum technology. All the proposed structures have used a single-layer layout without rotated cells. The suggested architecture is designed and validated based on the QCADesigner 2.0.3 tool. The findings revealed that all the developed circuits have a simple architecture with fewer quantum cells, optimal area, and low latency. [ABSTRACT FROM AUTHOR]