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Software-based attacks exploit bugs or vulnerabilities to get unauthorized access or leak confidential information. Dynamic information flow tracking (DIFT) is a security technique to track spurious information flows and provide strong security guarantees against such attacks. To secure heterogeneous systems, the spurious information flows must be tracked through all their components, including processors, accelerators (i.e., application-specific hardware components) and memories. We present PAGURUS, a flexible methodology to design a low-overhead shell circuit that adds DIFT support to accelerators. The shell uses a coarse-grain DIFT approach, thus not requiring to make modifications to the accelerator’s implementation. We analyze the performance and area overhead of the DIFT shell on field programmable gate arrays (FPGAs) and we propose a metric, called information leakage, to measure its security guarantees. We perform a design-space exploration to show that we can synthesize accelerators with different characteristics in terms of performance, cost, and security guarantees. We also present a case study where we use the DIFT shell to secure an accelerator running on an embedded platform with a DIFT-enhanced RISC-V core. [ABSTRACT FROM AUTHOR]

The RISC-V Instruction Set Architecture (ISA) is becoming an increasingly popular ecosystem for both hardware and software development. In this article, we investigate one of RISC-V’s most versatile ISA extensions, which allows for compressed 16-bit instructions to coexist with regular 32-bit instructions. While the use of instruction compression has been touted as a means to primarily reduce code density, we present another beneficial exploitation avenue: dual issuing of compressed 16-bit instructions with minimal hardware overhead. Consequently, the proposed RISC-V processor design can substantially improve instruction throughput and reduce execution times. Additionally, the new processor employs selective register renaming to specifically target the registers used under instruction compression, thereby completely eliminating unnecessary stalls due to name dependencies. Finally, the new design utilizes a partitioned register file that capitalizes on the skewed use of registers to improve energy efficiency through clock gating. Extensive hardware analysis and cycle-accurate simulations using real applications demonstrate the effectiveness of the proposed processor architecture. Dual issuing of compressed instructions is shown to often approach the performance of a full-width two-way superscalar processor, but with much higher area and power efficiency; this is of paramount importance to severely resource-restricted emerging paradigms, such as wearable devices and Internet-of-Things (IoT) environments. [ABSTRACT FROM AUTHOR]

This paper presents a dual-core lockstep (DCLS) implementation to protect hard-core processors against radiation-induced soft errors. The proposed DCLS is applied to an Advanced RISC Machine Cortex-A9 embedded processor. Different software optimizations were evaluated to assess their impact on performance and fault tolerance. Heavy ions’ experiments and fault injection emulation were performed to analyze the system susceptibility to errors and the DCLS performance. Results show that the approach is able to decrease the system cross section and achieve high protection against errors. The DCLS successfully protects the system from up to 78% of the injected faults. The execution performance analysis shows that by reducing the number of verifications and augmenting the block partition execution time, it is possible to increase the system reliability with minimal performance losses. [ABSTRACT FROM AUTHOR]

A model for a multichain polymer system in three-dimensional continuous space is studied by link cell Monte Carlo methods, using systems up to chain length N=64 and up to 16 384 monomers. The chains consist of beads with a hard core connected by rather stiff harmonic bonds, with a repulsive Lennard-Jones-type interaction between beads chosen such that chains cannot cross each other during their random motions. On RISC workstations the model performs only about a factor of 4 slower than the bond fluctuation lattice model, the qualitative behavior of the time-dependent mean-square displacements and relaxation functions being rather similar to the latter. For the model without obstacles, it is shown that the present continuum model can be approximately mapped on the lattice bond fluctuation model by a suitable rescaling of chain length and volume fraction. But the distinctive advantage of the present model is that it can be applied easily to random media (described by randomly placed rigid obstacles), without the severe ergodicity problems (locked-in configurations) arising in lattice models for such systems. It is shown that static properties of the chains stay nearly unaffected by the obstacles, while the chain motions are considerably slowed down in this frozen environment. [ABSTRACT FROM AUTHOR]

The fused-multiply-add (FMA) instruction is a common instruction in RISC processors since 1990. A 3-stage, 8-level pipelined, dual-precision FMA is proposed here that can perform operations either at one double precision (SISD) or at two single precision in parallel (SIMD). The 53-bit mantissa-multiplier (MM) is optimally segmented by Karatsuba–Offman (KO) algorithm such that both modes can be performed. The 6-stage pipelined MM uses only 6 of 10 multipliers and 13 of 33 adder/subtractors in SIMD. Thus hardware area of the proposed MM is reduced by 23.82% and throughput is maintained to be 923M samples/s. The arithmetic operational units in the data path are shared among the modes by having four data rearrangement units (DRU) which rearranges the data systematically at the input, the outputs of MM and the final output. Though these DRUs bring some hardware overhead, the resulting architecture is modular and uniform for both modes of computation. The proposed FMA has been implemented using TSMC 1P6M CMOS 130 nm library and takes 48% less overall area and consumes 49% less power at 308.7 MHz compared to previous results. The area-delay-product (ADP), 0.48 × 10 −15 shows that the area optimization by proposed KO based MM can also keep the computation time as 3.24 ns. [ABSTRACT FROM AUTHOR]

This paper presents the integration issues of a proposed run-time configurable Memory Management Unit (MMU) to the COFFEE processor developed by our group at Tampere University of Technology. The MMU consists of three Translation Lookaside Buffers (TLBs) in two levels of hierarchy. The MMU and its respective integration to the processor is prototyped on a Field Programmable Gate Array (FPGA) device. Furthermore, analytical results of scaling the second-level Unified TLB (UTLB) to three configurations (with 16, 32, and 64 entries) with respect to the effect on overall hit rate as well as the energy consumption are shown. The critical path analysis of the logical design running on the target FPGA is presented together with a description of optimization techniques to improve static timing performance which leads to gain 22.75% speed-up. We could reach to our target operating frequency of 200 MHz for the 64-entry UTLB and, thus, it is our preferred option. The 32-entry UTLB configuration provides a decent trade-off for resource-constrained or speed-critical hardware designs while the 16-entry configuration poses unsatisfactory performance. Next, integration challenges and how to resolve each of them (such as employing a wrapper around the MMU, modifying the hardware description of the COFFEE core, etc.) are investigated in detail. This paper not only provides invaluable information with regard to the implementation and integration phases of the MMU to a RISC processor, it opens a new horizon to our processor to provide virtual memory for its running operating system without degrading the operating frequency. This work also tends toward being a general reference for future integration to the COFFEE core as well as other similar processor architectures. [ABSTRACT FROM AUTHOR]

The final phase of CMOS technology scaling provides continued increases in already vast transistor counts, but only minimal improvements in energy efficiency, thus requiring innovation in circuits and architectures. However, even huge teams are struggling to complete large, complex designs on schedule using traditional rigid development flows. This article presents an agile hardware development methodology, which the authors adopted for 11 RISC-V microprocessor tape-outs on modern 28-nm and 45-nm CMOS processes in the past five years. The authors discuss how this approach enabled small teams to build energy-efficient, cost-effective, and industry-competitive high-performance microprocessors in a matter of months. Their agile methodology relies on rapid iterative improvement of fabricatable prototypes using hardware generators written in Chisel, a new hardware description language embedded in a modern programming language. The parameterized generators construct highly customized systems based on the free, open, and extensible RISC-V platform. The authors present a case study of one such prototype featuring a RISC-V vector microprocessor integrated with a switched-capacitor DC-DC converter alongside an adaptive clock generator in a 28-nm, fully depleted silicon-on-insulator process. [ABSTRACT FROM AUTHOR]

In recent years, several approaches have been developed to carry out biosensors based on localized surface plasmon resonance (LSPR). However, the high costs of nanostructure fabrication and the absence of autonomous portable devices strongly limit the extensive use of LSPR biosensors outside the research laboratories. We designed, implemented, and tested a novel low cost multiparametric stand-alone LSPR imaging instrument for biosensing applications. This compact device (15 × 6 × 17 cm3 size and <500-g weight) consists of a nanohole array biochip integrated with a microfluidic layer and a processing system. An optical apparatus focuses a light beam from an IR LED source and a digital image sensor captures the reflected light from the biochip surface. The signals are processed by the embedded ARM processor and shown on a touchscreen display by a user-friendly application, without the need for other external computational devices. Moreover, we propose an extremely simple analytical method to reduce the image noise without any sophisticated temperature control or external luminosity change compensation. The device sensitivity of 6 \times 10^\mathrm -5 refractive index unit was measured using glycerol solutions with different concentrations. We demonstrated the efficiency of our system in biomolecular detection by monitoring the Ab-PTX3 antibody in a test that showed the instrument’s potentialities in the detection of antibodies. These results confirmed the potential usefulness of the proposed system in several biomedical applications such as medical diagnostic procedures, immunoassays, or fast in loco preliminary analyses without the aid of specialized laboratory or trained personnel. [ABSTRACT FROM AUTHOR]

The modern embedded market massively relies on RISC processors. The code density of such processors directly affects memory usage, an expensive resource. Solutions to mitigate this issue include code compression techniques and ISAs extensions with reduced instructions bit-width, such as Thumb2 and MicroMIPS. This paper proposes a 16-bit extension to the SPARC processor, the SPARC16. Additionally, we provide the first methodology for generating 16-bit ISAs and evaluate compression among different 16-bit extensions. SPARC16 programs can achieve better compression ratios than other extensions, attaining results as low as 67%. Moreover, SPARC16 reduces cache miss rates up to 9%, requiring smaller caches than SPARC processors to achieve the same performance; a cache size reduction that can reach a factor of 16. [ABSTRACT FROM AUTHOR]

This paper presents a novel digital sinusoidal pulse-width modulation (SPWM) technique based on immediate calculation of duty cycle count (DCC) values of pulses with high speed Harvard architecture based RISC controllers. The DCC values are calculated with the multiplication of an instant modulation index count (MIC) and a preloaded sine count value (SCV) table in the program memory of the controller. The proposed technique overcomes the drawbacks of overhead time in digital carrier-reference based technique and large memory requirement in look-up table technique. The proposed technique is effective where frequent change of modulation index (MI) of SPWM is essential like grid-connected inverter applications. The effectiveness of the proposed technique is verified with both Proteus VSM based simulation and dsPIC based experiment. [ABSTRACT FROM AUTHOR]

Purpose – The purpose of this paper is to improve an image defogging algorithm based on a dark channel prior and use this method to clear the foggy image on the Advanced RISC (Reduced Instruction Set Computing) Machines (ARM) platform. Design/methodology/approach – The divided strategy of the foggy image was proposed through the estimation of the brightness and transmission thresholds. The two regions of the foggy image were processed using two transmissions. Many foggy images were tested using the improved method. Findings – The finding resulting from this study is that a divided strategy has been proposed to use the image defogging. Compared with the existing methods, the running time of the improved method is less on the ARM platform. Practical implications – Image enhancement is an important technology of digital images, and the quality of images plays a key role in the video monitoring and the intelligent transportation system. Originality/value – This paper presented an improved image defogging method using the divided strategy and a substantial number of experimental results was provided to demonstrate this method. [ABSTRACT FROM AUTHOR]

With the scaling of complementary metal-oxide-semiconductor (CMOS) technology to the submicron range, designers have to deal with a growing number and variety of fault types. In this way, intermittent faults are gaining importance in modern very large scale integration (VLSI) circuits. The presence of these faults is increasing due to the complexity of manufacturing processes (which produce residues and parameter variations), together with special aging mechanisms. This work presents a case study of the impact of intermittent faults on the behavior of a reduced instruction set computing (RISC) microprocessor. We have carried out an exhaustive reliability assessment by using very-high-speed-integrated-circuit hardware description language (VHDL)-based fault injection. In this way, we have been able to modify different intermittent fault parameters, to select various targets, and even, to compare the impact of intermittent faults with those induced by transient and permanent faults. [ABSTRACT FROM PUBLISHER]

This article describes the implementation of a web server using an embedded Altera NIOS II IP core, a general purpose and configurable RISC processor which is embedded in a Cyclone FPGA. The processor uses the µCLinux operating system to support a Boa web server of dynamic pages using Common Gateway Interface (CGI). The FPGA is configured to act like the master node of a network, and also to control and monitor a network of smart sensors or instruments. In order to develop a totally functional system, the FPGA also includes an implementation of the time-triggered protocol (TTP/A). Thus, the implemented master node has two interfaces, the webserver that acts as an Internet interface and the other to control the network. This protocol is widely used to connecting smart sensors and actuators and microsystems in embedded real-time systems in different application domains, e.g., industrial, automotive, domotic, etc., although this protocol can be easily replaced by any other because of the inherent characteristics of the FPGA-based technology. [ABSTRACT FROM AUTHOR]

This work proposes the development of an embedded real-time fruit detection system for future automatic fruit harvesting. The proposed embedded system is based on an ARM Cortex-M4 (STM32F407VGT6) processor and an Omnivision OV7670 color camera. The future goal of this embedded vision system will be to control a robotized arm to automatically select and pick some fruit directly from the tree. The complete embedded system has been designed to be placed directly in the gripper tool of the future robotized harvesting arm. The embedded system will be able to perform real-time fruit detection and tracking by using a three-dimensional look-up-table (LUT) defined in the RGB color space and optimized for fruit picking. Additionally, two different methodologies for creating optimized 3D LUTs based on existing linear color models and fruit histograms were implemented in this work and compared for the case of red peaches. The resulting system is able to acquire general and zoomed orchard images and to update the relative tracking information of a red peach in the tree ten times per second. [ABSTRACT FROM AUTHOR]

This work presents a static method implemented in a compiler for extracting high instruction level parallelism for the 32-bit QueueCore, a queue computation-based processor. The instructions of a queue processor implicitly read and write their operands, making instructions short and the programs free of false dependencies. This characteristic allows the exploitation of maximum parallelism and improves code density. Compiling for the QueueCore requires a new approach since the concept of registers disappears. We propose a new efficient code generation algorithm for the QueueCore. For a set of numerical benchmark programs, our compiler extracts more parallelism than the optimizing compiler for an RISC machine by a factor of 1.38. Through the use of QueueCore's reduced instruction set, we are able to generate 20% and 26% denser code than two embedded RISC processors. [ABSTRACT FROM AUTHOR]

This paper proposes a new architecture for EIA-709.1 protocol implementation. The protocol is conventionally implemented with the proprietary processor and language, Neuron chip and Neuron C, respectively, where the Neuron chip consists of 3 processors inside. The proposed architecture uses only one general purpose processor and general ANSI C to implement the layers of EIA-709.1 except the physical layer. The data link, network, and other layers are implemented onto one RISC processor, ARM. Specifically, the data link layer of the EIA-709.1 based on predictive p-persistent CSMA/CA is implemented. The interface between the transceiver based on power line communication and the data link layer based on the ARM is described. As a conclusion, this research shows the improvement of performance and the compatibility with the existing Neuron chip. [ABSTRACT FROM AUTHOR]

Abstract: In an attempt to improve the speed of VLSI signal processing systems, a new architecture for a high-speed multiply–accumulate (MAC) unit optimized for digital filters is proposed. This unit is designed as a coprocessor for the LEON2 RISC processor [LEON2 Processor; 2005 [Online]. ]. In this work, four parallel MAC units with two dual-port coefficient register-files, a three-port general register-file and a control unit are included in the coprocessing block. With the existence of four parallel units, several SIMD format instructions have been added to LEON2 instruction set. Each MAC unit has two 16-bit inputs, 32-bit output register and a programmable round-saturate block. The MAC unit uses a new architecture which embeds the accumulate module within the partial products summation tree of the multiplier with minimum overhead. A central control unit controls inputs of the four MACs and loading of the output registers. Our experimental results demonstrate a high performance in implementation of digital filters at elevated speeds of up to 33 millions of input samples per second in a 0.18μm technology. [ABSTRACT FROM AUTHOR]

Soft error is becoming increasingly important in the era of sub-100 nanometer very large scale integrated (VLSI) circuits. This article focuses on the impact of soft error on an OpenRisc 1200 CPU core. A C++ programming language based soft error analysis tool, with the name of SERSim, is created to perform a detailed exploration of this impact. The estimation error of SERSim ranges from 0.1% to 4.5%. With the help of SERSim, we find out that almost all the glitch widths are narrower than 200 ps in a 45 nm OpenRisc 1200 microprocessor circuit. This result is important for soft error rate reduction of VLSI circuits. The outputs of the multiplier of the OpenRisc 1200 microprocessor are found to be the most troublesome. Those outputs, which represent only 3% of the circuit outputs, produce more than half of the circuit bit error rate. A significant impact of performance requirements on circuit vulnerability to soft error is observed in our experiment. The difference helps us to analyse the estimation error of high-level soft error models. [ABSTRACT FROM AUTHOR]

Abstract: Java has gained great popularity in embedded appliances such as set-top boxes, smart phones and other hand held devices. In this paper we propose a translation based hw/sw codesigned Java virtual machine architecture, which extends a typical embedded RISC processor. The architectural extensions we propose include special instructions that accelerate translated blocks dispatch and security checks for arrays and objects. The extensions are done in a way that operating systems support is maintained, something that makes their adoption more attractive. Benchmarking using Embedded Caffeine Mark (ECM) benchmarks, showed significant speedups, especially when high performance RISC processors are employed. [Copyright &y& Elsevier]

Abstract: This paper presents the design, implementation and performance evaluation of a coarse-grain dynamically reconfigurable FPGA platform for multi-service edge and access network devices. The platform consists of two MicroBlaze RISC processors and a number of hardware co-processors used for the processing of packet payloads (Data Encryption Standard (DES) and Lempel–Ziv Compression). The co-processors can be connected either directly to the processors or using a shared bus. The functionality of the co-processors is dynamically reconfigured to meet the requirements of the network workload. The system has been implemented on the Xilinx Virtex II Pro platform and the network traces from real passive measurements have been used for performance evaluation. The use of dynamically reconfigurable co-processors for network applications shows that the performance speedup versus a static version varies from 12% to 35% in the best case and from 10% to 15% on average, depending on the network traffic fluctuation. [Copyright &y& Elsevier]

The article explains the development and function of the Godson-3, a multicore reduced-instruction-set-computing (RISC) processor with hardware support for x86 emulation. The Godson-3 is a third-generation product in a series of microprocessors developed by the Institute of Computing Technology at the Chinese Academy of Sciences. The Godson-3 was engineered for high-throughput server applications and high performance scientific computing. Hardware support for the floating-point format and register is examined.

Reduced energy consumption is one of the most important design goals for embedded application domains like wireless communication, multimedia, and biomedical applications. The instruction memory hierarchy has been proven to be one of the most power hungry parts of the system. This paper introduces an architectural enhancement for the instruction memory to reduce energy consumption and improve performance. The proposed distributed instruction memory organization requires minimal hardware overhead and supports the execution of multiple incompatible loops in parallel in a uniprocessor system. We present different methods to implement the loop controller architecture, compare them, and show that distributing the instruction memory helps to reduce the interconnect cost as well. This architecture enhancement can reduce the energy consumed in the instruction memory hierarchy by 59 percent and improve the performance by 22 percent compared to hardware-based enhanced-SMT-based architectures. [ABSTRACT FROM AUTHOR]

Abstract: Modern cellular networks allow users to transmit information at high data rates, have access to IP-based networks deployed around the world, and access to sophisticated services. In this context, not only is it necessary to develop new radio interface technologies and improve existing core networks to reach success, but guaranteeing confidentiality and integrity during transmission is a must. The KASUMI block cipher lies at the core of both the f8 data confidentiality algorithm and the f9 data integrity algorithm for Universal Mobile Telecommunications System networks. KASUMI implementations must reach high performance and have low power consumption in order to be adequate for network components. This paper describes a specialized processor core designed to efficiently perform the KASUMI algorithm. Experimental results show two orders of magnitude performance improvement over software only based implementations. We describe the used design technique that can also be applied to implement other Feistel-like ciphering algorithms. The proposed architecture was implemented on a FPGA, results are presented and discussed. [Copyright &y& Elsevier]

This work presents a detailed case study in customizing a configurable, extensible, 32-bit RISC processor with vector/SIMD instruction extensions for the efficient execution of block-based video-coding algorithms utilizing a proprietary co-design environment. In addition to the default Full-Search motion estimation of the MPEG-2 Test Model 5, fourteen fast ME algorithms were implemented in both scalar and vector form. Results demonstrate a reduction of up to 68% in the dynamic instruction count of the full search-based encoder whereas the fast motion estimation algorithms achieved a reduction in instruction count of nearly 90%, both accelerated via three 128-bit vector/SIMD instructions when compared to the scalar, reference implementation of the standard. We address in detail the profiling, vectorization and the development of these vector instruction set extensions, discuss in depth the implementation of a parametric vector accelerator that implements these instructions and show the introduction of that accelerator into a 32-bit RISC processor pipeline, in a closely-coupled configuration. [Copyright &y& Elsevier]

Second year Computer Science students at the University of Manchester taking the VLSI Systems Design course complete the design of a 16-bit RISC processor down to silicon as the course laboratory exercise. Since the emphasis is on the design processes and testing, no especial effort is made to minimise power. This paper analyses the power dissipation of a typical pipelined design and then examines how the power efficiency might be improved at the architectural, RTL and logic levels. Simulation shows that the minimum dissipation is achieved by careful hand design; here, a factor of two improvement in the dissipation is achieved, with the major contribution being the logic level optimisation of the Register Bank to reduce the switching activity. [Copyright &y& Elsevier]

Single-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. The cross section of the 90 nm SOI processors is smaller than results for 130 and 180 nm counterparts, but the threshold is about the same. The scaling of the cross section with reduction of feature size and core voltage for SOI microprocessors is discussed. [ABSTRACT FROM AUTHOR]

Abstract: Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40nm gate length (LGATE) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and LGATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI. [Copyright &y& Elsevier]

The well-known models and concepts of functional testing of microprocessors are described. The properties of the RISC-architecture that aid in applying effective approaches to hardware testing are stated. Functional decomposition is used to develop a sequence of actions implemented in designing tests. Special attention is paid to testing of control units. The RISC-architecture has shown to be helpful in designing effective algorithms for testing at the architectural level. The designed procedures detect most of the defects in control circuits indirectly through data processing and storing devices without the use of control units. [ABSTRACT FROM AUTHOR]

The utility of a synthetic jet ejector for thermal management at low flow rates is discussed. A synthetic jet ejector typically consists of a primary "zero-mass-flux" unsteady jet driving a secondary airflow through a low profile, high aspect ratio channel. A simple configuration of a nominally two-dimensional jet ejector in a rectangular channel is used to investigate the effects of channel width on the induced flow rate, power dissipated, heat transfer coefficient and thermal efficiency. An active heat sink for high power microprocessors is developed using the jet ejector concept and its performance is discussed. [ABSTRACT FROM AUTHOR]

This article presents a method for fast fault injection into switch-level circuits using FPGA chips. In this method, gates model switch-level circuits and we can emulate mixed gate-switch-level models. By the use of this method, FPGA chips can be used to accelerate the fault-injection campaigns into switch-level models. The approach has been evaluated experimentally by injecting a set of faults into a pipelined RISC processor. The experimental results show that significant speed-ups with respect to fully simulation-based fault-injection methods can be achieved. [Copyright &y& Elsevier]

Presents a study which proposed optimization techniques to implement MPEG audio decoding algorithms in real-time using general-purpose 32-bit micro-controller unit RISC processor. Design methodology of MPEG-audio decoders; Implementation of software optimization processes and techniques; Results.

Looks at the Radio Frequency identification-enabled μ-chips, a data storage that act as an automatic identification device for manufactured goods. Advantages of the chip over other identification and tracking systems; Capabilities of the chip; Challenges in using μ-chip.

Presents information on a study which described a Level 3 BLAS computational kernels called the RISC BLAS, designed to be efficient on reduced-instruction-set computer (RISC) processors. Information on Level 3 BLAS; Implementation of kernels using both blocking and loop unrolling.

Describes the philosophy behind the development of the Montage architecture. Key architectural features of Montage; Functions of the MediaLink interface; Architectural modeling and instantiation. INSETS: Visualization: See what really happens;Vector3D in action.

Introduces Mitsubishi's D30V/MPEG multimedia processor which integrates a dual-issue reduced instruction set computer (RISC) with minimal hardware support to implement a real-time MPEG-2 decoder. Features of decoding chip; Implementation of high-speed instruction; Results of SPICE simulation. INSET: Acronyms.

Focuses on the low-power features of the M.CORE micro-reduced instruction set computer (RISC) architecture. Description of dual-processor solution for a time division multiple access baseband transceiver; Implementation of the M.CORE in a cellular baseband transceiver; Progress in the wireless communications industry. INSET: Definitions.

An accurate and safe estimation of a task's worst case execution time (WCET) is crucial for reasoning about the timing properties of real-time systems. In RISC processors, the execution time of a program construct (e.g., a statement) is affected by various factors such as cache hits/misses and pipeline hazards, and these factors impose serious problems in analyzing the WCETs of tasks. To analyze the timing effects of RISC's pipelined execution and cache memory, we propose extensions to the original timing schema where the timing information associated with each program construct is a simple time-bound. In our approach, associated with each program construct is worst case timing abstraction, (WCTA), which contains detailed timing information of every execution path that might be the worst case execution path of the program construct. This extension leads to a revised timing schema that is similar to the original timing schema except that concatenation and pruning operations on WCTAs are newly defined to replace the add and max operations on time-bounds in the original timing schema. Our revised timing schema accurately accounts for the timing effects of pipelined execution and cache memory not only within but also across program constructs. This paper also reports on preliminary results of WCET analysis for a RISC processor. Our results show that tight WCET bounds (within a maximum of about 30% overestimation) can be obtained by using the revised timing schema approach. [ABSTRACT FROM AUTHOR]

Presents the architectural design and very large scale integration implementation of a highly-reconfigurable data flow reduced instruction set computer processing element. Characteristics of static and dynamic data flow models; Gate-level implementation.

Investigates the performance of the memory hierarchy of RISC-systems for implementations employing three-dimensional technology. Modeled temperature variations; Architectural constraints of conventional implementations; Performance model; Access time of a direct-mapped and a two-way set-associated cache.

Presents a comparative study of the interconnect structure of a RISC processor/cache system. Performance potential of three-dimensional integrated circuits for high performance computer systems; Signal interconnection structure; Parameters; Modeling of interconnection lines and electrical package parameters.

Presents the Hewlett-Packard PA-8000 Reduced-instruction-set computer (RISC) central processing unit (CPU). Enhancements of the Precision Architecture (PA) 2.0; Features of the PA-8000 hardware; Characteristics of the physical chip; Resolution of scheduling problems using the instruction reorder buffer.

Focuses on the PowerPC AS A10 64-bit RISC microprocessor, which uses IBM CMOS 5L 0.5-micronm, 3-V, four-level-metal ASIC technology. Support for the PowerPC architecture; Enhancement of chip density and speed through the use of custom macros and multiport arrays; Reduction of chip-to-chip clock skew; Superscalar design of the microprocessor; Performance configurations.

Considers the problem of verification and testing of architectural timing models coded to predict cycles-per-instruction (CPI) performance of advanced CMOS superscalar RISC processors. Cause-effect relationships in terms of model defects and the associated fault signatures; Real-application-based test loop kernels; Specially designed synthetic test sequences.

This article presents information regarding network processors (NP) for future high-end systems and applications. As the global economy changes, time to market is becoming a dominant concern in the networking world. The networking and telecommunication industry, after a major market correction over the last four years, reveals solid signs of recovery. Nowadays, it is extremely important for manufacturers to pre- sent, in a timely fashion, innovative, well- defined, flexible, and low-cost products, which will diversify and distinguish them from the competition. Furthermore, many NPs incorporate hardware micro engines having a behavior resembling that of a simple RISC microprocessor. Such components provide specialized operations for network processing and extensive features for high-level software programmability It is critical for these components to effectively support many network services, including the provision of an acceptable quality of service. Thus, NPs support the execution of network-specific functions at very high speeds, while remaining flexible because of their programmability. A network end-to-end path involves several such active nodes, each able to process high-bandwidth data, ranging from a few megabits to several gigabits.