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The multi-component glass system has a composition of 10K2O–10ZnO–55 B2O3–(25–x)V2O5–xBi2O3 (x = 4, 5, 7.5, 9, 10 mol%) are synthesized by the melt-quenching method. Using X-ray diffraction examination, the amorphous phase in the material was confirmed. The physical characteristics of the produced compositions are examined using density (D) and molar volume (Vm). Calculations of physical properties showed that adding Bi2O3 from 4 to 10 mol% increased the glass density from 2.7878 to 3.3617 g cm−3 and decreased the molar volume from 40.4196 to 38.5895 cm3/mol. Studies of glass samples using the FTIR show bands of absorption for oxides in different structural groups. Octahedral [ BiO 6 ], [ BO 4 ], and tetrahedral [ BO 3 ] structural units are observed in the present glass matrices. The cutoff wavelength ( λ C ), and optical band gap energy were determined using UV absorption spectra. The increase in non-bridging oxygens can be linked to the decrease in optical band gap energy ( E opt ) (direct and indirect) and the increase in cutoff wavelength with an increase in Bi2O3 content. This is attributed to the existence of bismuth ions and the creation of non-bridging oxygens. Besides that, the values of optical parameters, viz., optical electronegativity, refractive index, and molar refractivity, are calculated. The metallization criterion values are less than 1 and the glass samples exhibit an increased tendency towards metallization. Both the conductivity and the dielectric constant increase with the rise in Bi2O3 content, however, the dielectric loss and the impedance reduce. The behavior and values of conductivity for the studied glasses reveal the semiconducting properties of all glass samples. These results suggest that the produced glass samples may be employed as amorphous semiconductors in electronics and memory switching devices. [ABSTRACT FROM AUTHOR]

...-ispotty-byte error correcting codes over Zq [7] are non-binary codes generalizing the binary irregular-spotty-byte codes [3] suitable for semiconductor memories in which a word is divided into irregular bytes not necessarily of the same length. The distance between distinct words is measured in terms of newly defined ... - metric function [7]. In this paper, we present the code construction methods of ...-ispotty-byte error correcting codes in terms of their parity check matrix. [ABSTRACT FROM AUTHOR]

With the development of electronic technology, semiconductor memory is gradually shifting toward smaller area with less power consumption. SOT-MRAM is one of the competitive substitutes for DRAM and SRAM due to its superior endurance and switching speed. In contrast to STT-MRAM, the separation of read and write routes allows SOT-MRAM to have a lower error rate and higher lifetime, but this comes at the expense of the memory density. In recent years, vertical integrated circuits have relied on TSV to complete 3D stacking to ease the pressure of Moore's Law on scaling circuits. SOT-MRAM can take advantage of 3D stacking to reduce power and latency. More importantly, the density of SOT-MRAM can be improved at the same time. In the paper, simulation is conducted based on DESTINY, with the TSV model supplemented to NVSIM to evaluate the performance of MRAM 3D structures. The 3D SOT-MRAM structure in DESTINY can be implemented with a bus layer and interconnect structure between layers, which greatly reduces the expense of area. However, the 3D structure requires a more complex interconnect structure to truly meet the requirements of high density. For this reason, 3D model of unit interconnection using TSV is presented in the paper. Memory has several components, of which the memory array is the one with the largest area share. This paper explores the spatial structure of the array and proposes a new model which allows more complex interconnect structures to be accomplished on the same area. [ABSTRACT FROM AUTHOR]

In this theoretical study, we explore the use of quantum code-based memories to enhance the lifetime of qubits and exceed the break-even point, which is critical for the implementation of fault-tolerant quantum computing. Specifically, we investigate the quantum phase-flip repetition code as a quantum memory and theoretically demonstrate that it can preserve arbitrary quantum information longer than the lifetime of a single idle qubit in a dephasing-time-limited system, e.g. in semiconductor qubits. Our circuit-based analytical calculations show the efficiency of the phase-flip code as a quantum memory in the presence of relaxation, dephasing, and faulty quantum gates. Moreover, we identify the optimal repetition number of quantum error correction cycles required to reach the break-even point by considering the gate error probabilities of current platforms for quantum computing. Our results provide guidelines for developing quantum memories in semiconductor quantum devices. [ABSTRACT FROM AUTHOR]

Soft errors are the primary concern in space and terrestrial integrated circuit applications. When a charged particle from space collides with a scaled memory circuit, a transient pulse is generated across the sensitive storage node, causing a bit flip throughout the storage nodes. This bit flip is stated as a soft error, which affects the semiconductor memory architecture's stability and reliability. This paper presents a 10 T SRAM (STS-10 T) cell that mitigates soft error challenges even at space temperature. To demonstrate the relative performance of the STS-10 T, existing radiation-hardened memory cells, such as the Quatro-10 T, PS10T, NS-10 T, RHBD-10 T, 10 T-SRAM, RHMD-10 T, QUCCE-10 T, and SIS-10 T, were evaluated. The read stability of the proposed STS-10 T memory cell is 2.6x/ 3x/ 1.5x/ 1.4x/ 1.25x/ 1.6x/ 2.03 × greater than that of the existing Quatro-10 T/ NS-10 T/ PS-10 T/ RHBD-10 T/ RHMD-10 T/ QUCCE-10 T/ SIS-10 T memory cells, respectively. Moreover, 1.48x/ 1.17x/ 1.18x/ 1.4x/ 1.01x/ 1.27x/ 1.45x/ 1.43 × greater write ability than Quatro-10 T/ NS-10 T/ PS-10 T/ RHBD-10 T/ 10 T-SRAM/ RHMD-10 T/ QUCCE-10 T/ SIS10T. In addition, when the supply voltage is at 1 V, the read and write access time, hold power, and critical charge is also improved. [ABSTRACT FROM AUTHOR]

The eutectic structure of metals and ceramics is the result of a self‐organization phenomenon in which multiple solid phases solidify with an ordered structure from a liquid phase. Hence, a melt‐solidification process was the only way to generate ordered structures in a ceramic eutectic system. Here, we prepared ordered structures of Y3Al5O12 (YAG)–Al2O3 composites via chemical vapor deposition in the YAG–Al2O3 eutectic system. Spatially periodic YAG rod and lamellar structures were generated in an alumina matrix homoepitaxially grown on the sapphire substrates on the Al2O3‐rich side of the eutectic composition, whereas α‐Al2O3 rod and lamellar structures were generated in a YAG matrix on the Y2O3‐rich side. The results reveal that the pattern formation of ordered structures in a ceramic eutectic system can occur not only during in the melt‐solidification process but also during the vapor deposition process. The Ce3+‐doped YAG–Al2O3 composite film converts some of the blue light into yellow light, allowing some of it to pass through, and emitting white light. The Eu3+‐doped YAG–Al2O3 composite film can be utilized as a scintillation screen for a high‐resolution X‐ray imaging test to see though a semiconductor storage device. [ABSTRACT FROM AUTHOR]

The next‐generation semiconductor memories are essentially required for the advancements in modern electronic devices. Ferroelectric memories by HfO2‐based ferroelectric thin films (FE‐HfO2) have opened promising directions in recent years. Nevertheless, improving the polarization switching speed of FE‐HfO2 remains a critical task. In this study, it is demonstrated that the composition‐graded Hf1‐xZrxO2 (HZO) ferroelectric thin film has more than two times faster polarization switching speed than the conventional composition‐uniform one. Meanwhile, it has excellent ferroelectricity and improved endurance characteristics. It is also discovered that when the HZO thin film has a gradient composition, the polarization‐switching dynamics shifts from the nucleation‐limited‐switching mechanism to the domain‐wall growth mechanism. Moreover, the transition of switching dynamics is responsible for the faster speed and better endurance of the composition‐graded HZO thin film. These findings not only reveal the physical mechanisms of this material system but also provide a new strategy for memory devices having faster speed and higher endurance. [ABSTRACT FROM AUTHOR]

The memory module is a semiconductor product fabricated by mounting several memory chips on a printed circuit board. In the module test, which is the final step in the memory module manufacturing process, the memory module is tested if it properly functions in the end-user system environment. Then, the chips in the memory module are individually checked for defects to guarantee that the quality matches consumers’ expectations. In this study, we propose a framework to predict which chips are defective in module tests using wafer and package test data. However, several challenges must be overcome. First, two different data modalities (i.e., tabular and image data) exist, which influence defect prediction differently for different chips. Second, the module test results are highly imbalanced, with a very low defect rate. To address these challenges, we use a multimodal fusion model that integrates the two different modalities by dynamically evaluating the informativeness of each modality. In addition, we adopt a technique to modify the loss function to be Fisher consistent to minimize the balanced error rate. We demonstrate that the proposed framework can effectively predict chip-level defects in module tests using a real dataset collected from a global semiconductor manufacturing company. [ABSTRACT FROM AUTHOR]

We fabricate top-gate transistors on the three-layer molybdenum disulfide (MoS2) with three, two, and one layers in the source and drain regions using atomic layer etching (ALE). In the presence of ALE, the device at zero gate voltage can exhibit high and low levels of drain current under the forward and reverse gate bias, respectively. The hysteresis loop on the transfer curve of transistor indicates that two distinct charge states exist in the device within a range of gate bias. A long retention time of the charge is observed. Unlike conventional semiconductor memories with transistors and capacitors, the two-dimensional (2D) material itself plays two parts in the current conduction and charge storage. The persistent charge storage and memory operation of the multilayer MoS2 transistors with thicknesses of a few atomic layer will further expand the device application of 2D materials with reduced linewidths. [ABSTRACT FROM AUTHOR]

Resistive random access memories with self-rectifying behaviors, in which the sneak-path issue in passive crossbar arrays can be alleviated without additional access devices, have been investigated recently. The applications of p-type transparent oxide semiconductors as a memory medium will pave the way for realizing all-transparent memories and integrating on the complementary metal-oxide-semiconductor devices. Here, Ag-based p-type delafossite AgCr 1 − x Mg x O 2 thin films were prepared onto n-Si wafers to investigate the resistive switching (RS) performance. Bipolar RS with self-rectifying behaviors were observed in the Au / AgCr 0.92 Mg 0.08 O 2 / n − Si sandwich structure, showing improved rectification ratio, On/Off ratio, and switching durability. The change of the oxygen vacancy concentration resulting from Mg doping plays a key role in determination of the RS. The intrinsic rectifying behavior in the low resistance state is attributed to the existence of a Schottky-like barrier in the AgCr 1 − x Mg x O 2 / n − Si p-n heterojunction. The RS behavior originates from the modification of the barrier, which is induced by the trapping/detrapping of charge carriers in oxygen vacancies at the interface. The results will provide novel RS devices based on p-type transparent delafossite thin films with a self-rectifying feature. [ABSTRACT FROM AUTHOR]

The study considers the impact of the environmental contamination by the electromagnetic radiation of electron beam generator and high-energy radioactive source on the memory components. Electron beam generator can be used for injecting particle energy into the plasma of the fusion system based on a Marx generator, while radioactive source as a simulator of high-energy ionizing radiation that can be caused by the neutron-induced activation of plasma surrounding structures or released from deuterium-tritium fusion reaction. The effects of gamma radiation of high-energy radioactive source and electric field of the electron beam generator on EPROM and EEPROM semiconductor computer memory, were investigated. An older memory types were deliberately chosen for the reason that their more robust construction will better protect them from the effects of ionizing and non-ionizing radiation. The results obtained under well-controlled conditions show a high degree of non-resistance of the semiconductor technology to the expected electromagnetic pollution of the electron beam generator and high-energy radioactive source. This conclusion raises doubts on the possibility of simultaneous application of electron beam generator, consequently fusion system and nanotechnologies with the increasing need for miniaturization of electronic components. [ABSTRACT FROM AUTHOR]

As a nanoscale semiconductor memory device, a ferroelectric memristor has promising prospects to break through the von Neumann framework in terms of artificial synaptic function, information processing, and integration. This study presents the fabrication of Li0.09Bi0.91FeO3 as the functional layer for a memristor device based on the Si substrate, enabling the integration of silicon complementary metal oxide semiconductor technology. In addition, it exhibits bipolar resistance switching characteristics in a direct current mode and can rapidly achieve stable conductance tunability at higher frequencies through the applied pulse for biosynapse simulation. More importantly, multiple devices are connected into electrical circuits to realize storage functions with information processing and programmable characteristics. This work paves the way for near-future applications of ferroelectric memristors in information processing. [ABSTRACT FROM AUTHOR]

There is a significant need to build efficient non-von Neumann computing systems for highly data-centric artificial intelligence related applications. Brain-inspired computing is one such approach that shows significant promise. Memory is expected to play a key role in this form of computing and, in particular, phase-change memory (PCM), arguably the most advanced emerging non-volatile memory technology. Given a lack of comprehensive understanding of the working principles of the brain, brain-inspired computing is likely to be realized in multiple levels of inspiration. In the first level of inspiration, the idea would be to build computing units where memory and processing co-exist in some form. Computational memory is an example where the physical attributes and the state dynamics of memory devices are exploited to perform certain computational tasks in the memory itself with very high areal and energy efficiency. In a second level of brain-inspired computing using PCM devices, one could design a co-processor comprising multiple cross-bar arrays of PCM devices to accelerate the training of deep neural networks. PCM technology could also play a key role in the space of specialized computing substrates for spiking neural networks, and this can be viewed as the third level of brain-inspired computing using these devices. [ABSTRACT FROM AUTHOR]

Since research on artificial intelligence has begun receiving much attention, interest in efficient hardware that can process a complex and large amount of information has also increased. The existing von Neumann computing architecture has significant limitations in terms of speed and energy efficiency. Volatile memristors are the most promising among several emerging memory semiconductor devices, because they have various features suitable for neuro-inspired applications. Therefore, a comprehensive review of volatile memristors is urgently needed for future research. Herein, we present the physical interpretation and latest research trends of the switching mechanisms of volatile memristors. We also review diverse promising applications using volatile memristors. In particular, we focus on selectors for array structures, synaptic devices for neuromorphic engineering, imitation of nociceptors, and reservoir computing for time-dependent input data processing. Finally, we discuss the future directions of volatile memristors and their applications. [ABSTRACT FROM AUTHOR]

In the fast-paced development of life in today's society, the use of ECG signals is not only used in the medical direction to scan patients; portable ECG signal acquisition tools can collect and analyze the corresponding ECG signals in time and respond to the wearer in time, so that the user can make timely adjustments or seek medical treatment in time to avoid a malignant situation that occurs. For people in sports, the collection of ECG signals is more helpful to the arrangement and estimation of training conditions. Based on nonvolatile memory technology, data will not be lost when the computer is turned off or suddenly or unexpectedly shut down. This research puts forward the design of an antiexercise ECG monitoring system that collects ECG signals for a group that is in the process of exercise. Use mathematical calculation system to classify, and conduct in-depth analysis of the reasons for poor anti-interference ability, and use the original denoising algorithm calculation as the basis to adapt to the dynamic situation in the opposite situation to the normal ECG signal acquisition in the static state. The collection is modified from the original basis. This research proposes an improved scheme for multichannel acquisition. Chips of semiconductor memory devices based on nonvolatile memory are embedded in mobile devices for use. The experimental results in this paper show that the comparison experiment ratio of collecting ECG signals from the sixth, third, fourth, and fifth directions can effectively reduce the mean square error (MSE), and the error of channel 6 is directly from 0.1598. It is down to 0.00143. Several other items showed a significant decrease. It shows that the anti-interference ability of the ECG monitoring system can be further enhanced by increasing the number of collection terminals. [ABSTRACT FROM AUTHOR]

To lower the charge leakage of a floating gate device and improve the operation performance of memory devices toward a smaller structure size and a higher component capability, two new types of floating gates composed of pn-type polysilicon or np-type polysilicon were developed in this study. Their microstructure and elemental compositions were investigated, and the sheet resistance, threshold voltages and erasing voltages were measured. The experimental results and charge simulation indicated that, by forming an n-p junction in the floating gate, the sheet resistance was increased, and the charge leakage was reduced because of the formation of a carrier depletion zone at the junction interface serving as an intrinsic potential barrier. Additionally, the threshold voltage and erasing voltage of the np-type floating gate were elevated, suggesting that the performance of the floating gate in the operation of memory devices can be effectively improved without the application of new materials or changes to the physical structure. [ABSTRACT FROM AUTHOR]

With the upcoming trend of Big Data era, some new types of memory technologies have emerged as substitutes for the traditional Si-based semiconductor memory devices, which are encountering severe scaling down technical obstacles. In particular, the resistance random access memory (RRAM) and magnetic random access memory (MRAM) hold great promise for the in-memory computing, which are regarded as the optimal strategy and pathway to solve the von Neumann bottleneck by high-throughput in situ data processing. As far as the active materials in RRAM and MRAM are concerned, organic semiconducting materials have shown increasing application perspectives in memory devices due to their rich structural diversity and solution processability. With the introduction of metal elements into the backbone of molecules, some new properties and phenomena will emerge accordingly. Consequently, the RRAM and MRAM devices based on metal-containing organic compounds (including the small molecular metal complexes, metallopolymers, metal–organic frameworks (MOFs) and organic–inorganic–hybrid perovskites (OIHPs)) have been widely explored and attracted intense attention. In this review, we highlight the fundamentals of RRAM and MRAM, as well as the research progress of the applications of metal-containing organic compounds in both RRAM and MRAM. Finally, we discuss the challenges and future directions for the research of organic RRAM and MRAM. [ABSTRACT FROM AUTHOR]

This paper considers a new model of error control codes for semiconductor memories consisting of RAM chips not necessarily of the same size. The information stored on a chip corresponds to a variable length byte and thus byte length is not same in this case and varies from chip to chip. The variable length byte is termed as a "general byte" or simply a "g-byte". The code presented in this paper are capable of correcting all single g-byte errors. [ABSTRACT FROM AUTHOR]

This study investigates the impact of channel thickness (T CH) variation on memory performance and its physical origins in vertical channel charge trap memory (V-CTM) using InGaZnO (IGZO) channels for X–Y scaling. When the T CH decreased, the subthreshold slope (SS) increased from 0.21 to 0.30 V/dec, while the minimum program voltage decreased from 12 to 8 V, indicating a performance trade-off. The analysis of bulk trap density extracted by SS, density of states distribution, and x-ray photoelectron spectroscopy confirmed an increase in the number of trap states and hydrogen-related defects in the IGZO channel when a thin T CH is employed. As a result, it was expected that the barrier height at the active layer/TL would be lowered during program operations at relatively thin channel. However, the SS would also be degraded due to an increase in sub-gap states, such as OH- and V O H, induced by hydrogen incorporation. The V-CTM with an optimal T CH of 7 nm had a maximum memory window of 5.7 V. The program/erase states were maintained for 106 s before experiencing a 50 % charge loss, and 5-level memory states were verified to be available within a memory window of 3.2 V for 108 s with little degradation. It was noteworthy that the long-term reliability and multilevel implementation could be secured for the V-CTM with a T CH as thin as 7 nm, demonstrating the sound feasibility of its X–Y scaling. This work presents new key parameters and understanding of device integration issues for future 3D structured memory transistors, and aims to contribute to the advancement of memory technologies using oxide semiconductor channels. • We fabricated a vertical channel charge trap memory with IGZO channel below 150 nm. • Channel thickness was modulated for X–Y scaling in the vertical channel structure. • Channel thickness control affected subthreshold swing and memory operation behavior. • In-depth analysis showed a correlation between channel thickness and hydrogen doping. • We propose insight for improving integration in oxide semiconductor channel memories. [ABSTRACT FROM AUTHOR]

A wafer bin map (WBM) represents the locational information of defective chips on the wafer. The spatial correlation of defects on the wafer provides crucial information for the root cause diagnosis of defects in wafer fabrication. The spatial correlation is classified as a defect pattern for efficient diagnostics. A defect pattern taxonomy should be defined in advance for coherent classification of defect patterns. Various taxonomies are used in previous studies, but they share common limitations in that the differentiation among defect patterns is unclear, the set of predefined defect patterns is insufficient, and they cannot accommodate newly-emerged defect patterns. A concept of spatial dimension-based defect pattern taxonomy and its development procedure are proposed. Defect patterns are defined by three spatial dimensions, namely, Shape , Size , and Location. The development procedure is applied to a major NAND flash memory semiconductor manufacturer for two years. Results show that spatial dimension-based taxonomy can improve the performance of the defect pattern classification system by alleviating common existing limitations. Moreover, meaningful defect patterns for diagnostics are retained through the engineers' involvement in the development procedure. [ABSTRACT FROM AUTHOR]

Spinel ferrites have a significant impact due to its physical and chemical properties. The solgel route has been employed in the present work, for achieving single phase nano-crystalline cobalt ferrites. All these samples were annealed with different temperatures from 600 °C to 900 °C in a muffle furnace. The FCC spinel structure of nanoparticles has been confirmed by powder x-ray diffraction (XRD) studies that demonstrate formation of crystalline size at various temperatures from 11-15 nm. The Raman spectroscopy revealed the characteristic absorption bands in 100 cm-1 to 700 cm-1 range where the graphs show five absorption bands and they confirmed the characteristic feature of spinel structure. With the help of Maxwell Wagner model, dielectric characterization has been carried out within a frequency range from 20 Hz to 20 MHz where dielectric parameters are found decreased with increasing the applied frequency. The alternating current conductivity phenomena increases with higher frequency ranges and show plane behavior in lower frequency ranges. The impedance mechanism, real and imaginary parts show decreasing trend on account of grain boundary activity. Interfacial polarization understood with the help of peaks obtained from the imaginary modulus pattern. These cobalt ferrite nanoparticles (CoFe2O4 NPs) are suitable to use in microwave devices, high frequency equipment, semiconductor devices and high storage media applications revealed by the dielectric studies. [ABSTRACT FROM AUTHOR]

In this study, we present programming speed enhancement in amorphous oxide semiconductor memory thin-film transistor (TFT). We developed a nonvolatile memory transistor based on InZnSnO back-channel-etch TFT with InGaZnO charge storage layer inserted between gate insulators. We proposed double-gate (DG) and body-contacted (BC) memory structure to improve memory erase speed, which is the most important issue in oxide memory TFTs. DG memory did not show sufficient improvement due to large voltage drop in second gate insulator. BC memory, which can control back-channel potential directly, showed significant improvement on memory program/erase speed. [ABSTRACT FROM AUTHOR]

The present day electronic gadgets have semiconductor memory devices to store data. The static random access memory (SRAM) is a volatile memory, often preferred over dynamic random access memory (DRAM) due to higher speed and lower power dissipation. However, at scaling down of technology node, the leakage current in SRAM often increases and degrades its performance. To address this, the voltage scaling is preferred which subsequently affects the stability and delay of SRAM. This paper therefore presents a negative bit-line (NBL) write assist circuit which is used for enhancing the write ability while a separate (isolated) read buffer circuit is used for improving the read stability. In addition to this, the proposed design uses a tail (stack) transistor to decrease the overall static power dissipation and also to maintain the hold stability. The comparison of the proposed design has been done with state-of-the-art work in terms of write static noise margin (WSNM), write delay, read static noise margin (RSNM) and other parameters. It has been observed that there is an improvement of 48%, 11%, 19% and 32.4% in WSNM while reduction of 33%, 39%, 48% and 22% in write delay as compared to the conventional 6T SRAM cell, NBL, V DD collapse and 9T UV SRAM, respectively. [ABSTRACT FROM AUTHOR]

ULTRARAM™ is a III–V semiconductor memory technology which allows non-volatile logic switching at ultra-low energy (per unit area). This is achieved by exploiting triple-barrier resonant tunnelling (TBRT) through a series of InAs/AlSb heterojunctions specifically engineered for this purpose. Electrons tunnelling through the barriers at low bias are trapped in a floating gate, in which the presence or absence of charge defines the memory logic. Here, we report detailed non-equilibrium Green's functions simulations of the InAs/AlSb TBRT heterostructure, which is the principal source of ULTRARAM™'s extraordinary performance benefits. The effects of variations to the heterostructure layer thickness are investigated for performance optimization, and for assessing growth and process tolerances for commercial implementation on 12″ Si wafers. Trade-offs between power, speed, logic disturbance and data retention time are identified. Importantly, most one monolayer alterations to the tunnelling region show the required characteristics for ULTRARAM™ memory operation, thus some tolerance in any future commercial fabrication process is identified. [ABSTRACT FROM AUTHOR]

As a promising alternative to dynamic RAM, phase change memory (PCM) suffers from limited write endurance. Therefore, many research proposals on PCM security or reliability have focussed on the possible threat of wear‐out attacks from malicious applications. However, it is also found that the non‐volatile nature and the programming behaviour of PCM bring other security challenges to the memory system. The authors examine the potential risk of information leakage and theft in memory management for PCM‐based cloud server or multitenant systems. By observing the influence of process variation (PV) on PCM cell programming, they propose a fast and efficient in‐memory data obfuscation mechanism to defend against memory attacks or information leakage during page reallocation mandated by OS. With the capabilities of in‐memory data randomisation, the proposed SecuRAM avoids the long write latency of PCM cells to erase the content, and achieves higher data initialisation efficiency than conventional software solutions. Second, the proposed SecuRAM also provides a novel solution of fast in‐memory hardware fingerprinting and random number generation, which are common and essential security functions in encryption or access authentication to protect confidential memory data from attackers. Two novel techniques are proposed to generate signatures and random numbers: the first is based on partial programming, which works in the same way as bulk data randomisation; the second is loop‐counting, which is an overhead‐free method by reusing the cell programming mechanism in iterate‐write PCM devices. Through evaluation, SecuRAM shows a much better performance and energy‐efficiency than conventional measures for PCM memory. [ABSTRACT FROM AUTHOR]

During dynamic random access memory (DRAM) capacitor scaling, a lot of effort was put searching for new material stacks to overcome the scaling limitations of the current material stack, such as leakage and sufficient capacitance. In this study, very promising results for a SrTiO3 based capacitor with a record low capacitance equivalent thickness value of 0.2 nm at target leakage current are presented. Due to the material properties of SrTiO3 films (high vacancy concentration and low band gap), which are leading to an increased leakage current, a physical thickness of at least 8 nm is required at target leakage specifications. However, this physical thickness would not fit into an 18 nm DRAM structure. Therefore, two different new approaches to develop a new ZrO2 based DRAM capacitor stack by changing the inter-layer material from Al2O3 to SrO and the exchange of the top electrode material from TiN to Pt are presented. A combination of these two approaches leads to a capacitance equivalent thickness value of 0.47 nm. Most importantly, the physical thickness of <5 nm for the dielectric stack is in accordance with the target specifications. Detailed evaluation of the leakage current characteristics leads to a capacitor model which allows the prediction of the electrical behavior with thickness scaling. [ABSTRACT FROM AUTHOR]

BACKGROUND: Traditionally, X-ray systems for capturing moving objects consist of a continuous X-ray source and a detector that operates at a predetermined frame rate. OBJECTIVE: This study investigates the possibility of using pulsed X-ray source with an inductive energy storage device and a semiconductor opening switch for shooting moving objects. METHODS: The study uses a high-voltage pulse generator that has the following parameters namely, the pulse voltage amplitude up to 320 kV, the pulse current up to 240 A, the current pulse duration of about 50 ns, and the pulse repetition rate up to 2 kHz. The duration and intensity of glow for standard CsI:Tl and Gd2O2S:Tb X-ray phosphors after their irradiation with X-ray flashes of about 50 ns duration are investigated. After X-ray radiation is converted into light, the signal is recorded using semiconductor detectors. We acquired several images of an object moving at a speed of about 20 m/s. A semiconductor detector with phosphor, which operates in the mode of continuous signal accumulation, is used. RESULTS: When using the pulsed X-ray source and phosphors with a short afterglow, the individual frames can be obtained at the pulse repetition rate of several kilohertz, and the detector does not contain the residual luminescence from the previous frame by the arrival of the next frame. CONCLUSIONS: The X-ray source shows good pulse-to-pulse reproducibility of X-rays, and can be used to capture objects in motion at a frame rate of several kHz. [ABSTRACT FROM AUTHOR]

ULTRARAM is a III–V compound semiconductor memory concept that exploits quantum resonant tunneling to achieve nonvolatility at extremely low switching energy per unit area. Prototype devices are fabricated in a 2 × 2 memory array formation on GaAs substrates. The devices show 0/1 state contrast from program/erase (P/E) cycles with 2.5 V pulses of 500-μs duration, a remarkable switching speed for a 20 μm gate length. Memory retention is tested for 8 × 104 s, whereby the 0/1 states show adequate contrast throughout, whilst performing 8 × 104 readout operations. Further reliability is demonstrated via program-read-erase-read endurance cycling for 106 cycles with 0/1 contrast. A half-voltage array architecture proposed in our previous work is experimentally realized, with an outstandingly small disturb rate over 105 half-voltage cycles. [ABSTRACT FROM AUTHOR]

Frequently, soft errors occur due to striking of radioactive particles in memory cells which reduce the reliability of memory systems. Generally, single error correction-double error detection (SEC-DED) codes are employed to detect and correct the soft errors in semiconductor memory systems. In this paper, a new optimization algorithm is proposed based on common sub-expression elimination method. By employing this proposed optimization algorithm, more simplified expressions for encoder and decoder are obtained from parity check matrix (H-matrix). Proposed optimization technique has been used to implement seven different SEC-DED codecs with message length of 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, 256 bits and 512 bits. Compact design requires at most 21.66% lesser number of two-input XOR gates compared to related SEC-DED codes. All codec architectures are simulated and synthesized using both FPGA and ASIC platforms. Area and power consumption of proposed designs are reduced compared to the existing design without affecting its speed. Proposed designs are beneficial in computer memory systems due to its compactness and lower power consumption. [ABSTRACT FROM AUTHOR]

PCMs are Non-Volatile Memories (NVMs) that store data using phase-change semiconductors, such as silicon-chalcogenide glass. In addition to increased integration density, PCMs have high durability and data transfer rates and consume less power during read/write operations. Compared with flash memory, PCM operates at much faster speeds and is close to the performance of DRAM. As a result, it is one of the most popular semiconductor memories which is used in various applications. However, PCM cells are limited to a certain number of write operations, and because of that, values cannot be changed when this limit is reached. Hence, PCMs do not last for a long time. The limited lifespan of PCM memory has led to considerable research in recent years. Several architectural levels and methods have been offered and examined to overcome this challenge. In this study, functional and practical techniques are identified and analyzed to extend the longevity of PCMs. These schemes can also be used to prolong the life of other NVM technologies since they share similar characteristics with PCMs. Furthermore, we will present some improvements to PCM performance to make it competitive with common NVMs. In conclusion, this survey will be helpful to both researchers who are considering starting PCM projects and those already proficient in PCM. [ABSTRACT FROM AUTHOR]

When manufacturing systems on a chip using modern technologies with highly integrated elements, problems arise in testing and repairing the internal memory. The original architecture of the fault-tolerant semiconductor memory with the given failure detection rate is proposed. At the same time, rather than the entire device being backed up only the elements that are most susceptible to failures are backed up, which reduces its weight and cost. The fault-tolerant memory design with automatic recovery is verified after quadruple failures. The fault-tolerant memory project is implemented in the M2S010-TQ144 chip of the system based on the SF2-Junior-KIT chip in the integrated development environment of Microsemi Libero SoC v11.8. The proposed architecture of fault-tolerant memory ensures the automatic recovery from the multiple failures of elements onboard spacecraft control systems using a built-in self-healing device without the use of fusible jumpers and the participation of maintenance personnel. In the semiconductor memory, when faults are detected, the data bits of the main array of storage cells in which failures occur are automatically replaced with the data emerging from the outputs of the spare array of storage cells. This improves reliability when performing multiple recovery cycles. [ABSTRACT FROM AUTHOR]

When manufacturing systems on a chip using modern technologies with highly integrated elements, problems arise in testing and repairing the internal memory. The original architecture of the fault-tolerant semiconductor memory with the given failure detection rate is proposed. At the same time, rather than the entire device being backed up only the elements that are most susceptible to failures are backed up, which reduces its weight and cost. The fault-tolerant memory design with automatic recovery is verified after quadruple failures. The fault-tolerant memory project is implemented in the M2S010-TQ144 chip of the system based on the SF2-Junior-KIT chip in the integrated development environment of Microsemi Libero SoC v11.8. The proposed architecture of fault-tolerant memory ensures the automatic recovery from the multiple failures of elements onboard spacecraft control systems using a built-in self-healing device without the use of fusible jumpers and the participation of maintenance personnel. In the semiconductor memory, when faults are detected, the data bits of the main array of storage cells in which failures occur are automatically replaced with the data emerging from the outputs of the spare array of storage cells. This improves reliability when performing multiple recovery cycles. [ABSTRACT FROM AUTHOR]

The multi‐level feature of GeTe/Sb2Te3 interfacial phase change memory was achieved by applying a designed voltage‐based pulse. It stably demonstrated five multi‐level states without interference for 90 cycles by varying the pulse width. GeTe/Sb2Te3 interfacial phase change memory demonstrated retention time of > 1.0 × 103 s, presenting the significantly low drift coefficient (ν) of < 0.009, indicating no resistivity drift due to the structure relaxation of glass. In addition, the reset energy consumption of GeTe/Sb2Te3 interfacial phase change memory was reduced by more than 85% compared to conventional Ge2Sb2Te5 phase change memory at each bottom electrode contact size. Multi‐level‐cell operation mechanism and gradual increase in conductance value of GeTe/Sb2Te3 interfacial phase change memory was explained by a partial resistance transition model where phase transition occurred partially in all layers. The result of the GeTe/Sb2Te3 interfacial phase change memory performance is expected to bring great advantages to the next‐generation storage class memory industry that requires low energy and high density. [ABSTRACT FROM AUTHOR]

As a new type of semiconductor memory device, memristors receive wide attention because of their ability to realize multilevel memory and synapse-like learning. However, memristors made of traditional materials often demonstrate dispersion and unstable switching. Ferroelectric memristors can solve this problem and realize the regulation of synaptic plasticity. Herein, memristors based on Hf0.5Zr0.5O2 are fabricated on Si substrates. The I-Vcurve shows that the turn-on voltage of the device is lower for Hf0.5Zr0.5O2 film than for other compositions in HfxZr1-xOy films, and the ratio of ROFF/ RON can reach 104, implying excellent device performance. Furthermore, the train of pulse with different parameters can influence the modulation of device conductance. Also, the synaptic plasticity behavior of the device is studied. These results lay the foundation for the development of ferroelectric thin films with neuron-like artificial synapses. [ABSTRACT FROM AUTHOR]

This article reviews the resistive random-access memory (ReRAM) technology initialization back in the 1960s and its heavily focused research and development from the early 2000s. This review goes through various oxygen/oxygen vacancy and metal-ion-based ReRAM devices and their operation mechanisms. This review also benchmarks the performance of various oxygen/oxygen vacancy and metal-ion-based ReRAM devices with general trend drawn. Being a semiconductor memory and storage technology, the commercialization attempts for both stand-alone mass storage/storage-class memory and embedded nonvolatile memory are also reviewed. Looking toward the coming era, the potential of using ReRAM technology to improve machine learning efficiency is discussed. [ABSTRACT FROM AUTHOR]

In this paper, we investigate warm electron injection (WEI) as a mechanism for NOR programming of double-gate SONOS memories through two dimensional (2D) full-band Monte Carlo simulations. WEI is characterized by an applied VDS smaller than 3.15 V, so that electrons cannot easily accumulate a kinetic energy larger than the height of the Si/SiO2 barrier. We perform a time-dependent simulation of the program operation where the local gate current density is computed with a continuum-based method and is adiabatically separated from the 2D full Monte Carlo simulation used to obtain the electron distribution in the phase space. Trapping and detrapping from the nitride layer is taken into account by using a simplified Shockley–Read–Hall model. In this way, we are able to compute the time evolution of the charge stored in the nitride layer and of the threshold voltages corresponding to forward and reverse biases. We show that WEI is a viable option for NOR programming in order to reduce power supply and preserve reliability and complementary metal-oxide-semiconductor logic level compatibility. With the limitations of our adopted physical model, our results confirm the experimental observation showing that WEI provides a well localized trapped charge and offers interesting perspectives for multilevel and dual bit operation, even in devices with negligible short channel effects. [ABSTRACT FROM AUTHOR]

TiSi2/Si heteronanocrystals on ultrathin oxide was fabricated with self-aligned silicidation method. Compared with Si nanocrystal memory device, TiSi2/Si heteronanocrystal metal-oxide-semiconductor memory device shows higher writing saturation level, faster writing/erasing speed, longer retention, and larger memory window. Therefore, heteronanocrystals are very promising to replace Si nanocrystals for future nonvolatile memory applications. [ABSTRACT FROM AUTHOR]

Abstract Although oxide-based resistive switching memory (OxRAM) is one of the strong next-generation high-capacity memory candidates, it has an unresolved problem that the higher the resistance levels, the larger the cycle-to-cycle resistance variabilities to be operated in multi-resistance level mode. In this paper, we develop a simple theory from the operating principles of OxRAMs that excellently matches with experiments both qualitatively and quantitatively. From the theory, we can finally understand the fundamental capabilities of multi-resistance level operation of OxRAMs, and how to improve the switching properties within that. Highlights • For oxide-based resistance memories (OxRAM), resistance distribution patterns show some kind of a specific relation with its resistance levels. • From the theoretical analysis of statistical physics, it's shown that the experimentally measured resistance distribution can be explained near perfectly in theoretical perspective only. • This model might provide useful insight to more clearly understand the potential of OxRAM to be a powerful high-capacity memory device. [ABSTRACT FROM AUTHOR]

We propose SRAMs and DRAM with independent read–write paths employing phase transition material (PTM) in the read port to enable a more compact design compared to standardmultiport cells. Our technique employs 1) the orders of magnitude difference in the resistances of the insulating and metallic phases of the PTM and 2) regulated phase transitions to design a 7T single-ended SRAM, an 8T differential SRAM, and a 2T DRAM. Compared to previously proposed 8T SRAM, our 7T design achieves 9.1% less cell area and our 8T design achieves differential read without area penalty. We extensively analyze the material requirements for PTM to enable the proposed cell operation. We show that the read performance of the proposed 7T cell is only 5% worse than previously proposed standard 8T, while the proposed 8T design shows a 38% improvement. Similarly, our 2TDRAM cell achieves 20% less cell area than 3T DRAM, with less than 6% read time penalty. The benefits for all the designs come at no write overheads. [ABSTRACT FROM AUTHOR]

This paper introduces a high rate error-correcting coding scheme called symmetric block-wise concatenated Bose–Chaudhuri–Hocquenghem (symmetric BC-BCH) codes tailored for storage devices with hard-decision outputs, e.g., storage devices based on NAND flash memory. It will be shown that a careful integration of the symmetry and 2-D block-wise concatenation is especially beneficial to achieve improvements of error-rate performance when an iterative hard-decision-based decoding (IHDD) is assumed. The claim is substantiated by proving that the proposed symmetric concatenation is optimal in terms of error-rate performance in the low error-rate regime over other 2-D block-wise concatenations. Besides, this paper proposes a novel way to design constituent codes, which enables us to enjoy advantages of primitive BCH codes and to efficiently break stopping sets associated with the IHDD in the low error-rate regime. We consider error-control systems made up of a symmetric BC-BCH code, the IHDD, and simple auxiliary decoders specifically targeting to break stopping sets caused in the IHDD. It will be shown that the auxiliary decoders significantly improve error-rate performance at a negligible amount of extra complexity. Performance comparisons are also carried out between error-control systems with the proposed and other coding schemes such as BCH codes, quasi-primitive BC-BCH codes, and low-density parity-check codes. [ABSTRACT FROM AUTHOR]

Abstract: As the time for big data is coming, the demand for data's storage density and capacity exerts explosive growth. However, traditional optical storage is hard to get rid of the bottleneck of optical diffraction limit. The persistent luminescence materials could be used for optical data storage based on the photon trapping and de‐trapping mode. Herein the performance of thermoluminescence (TL), photo‐stimulated luminescence, and photoluminescence of Pr3+‐doped Ca4Ti3O10 were studied in order to explore the optical storage property of this material. The TL glow curves show that the deep‐trap in Ca4Ti3O10:0.01Pr3+, Y3+ has a narrow distribution from 0.9 to 0.98 eV, which is qualified for maintaining the recorded data at RT for a long duration time. NIR photo‐stimulated red persistent luminescence (NIR‐to‐red mode) as presented in the Y‐containing Ca4Ti3O10:Pr3+ phosphor could be a promising technique for optical data storage. [ABSTRACT FROM AUTHOR]

NAND flash memories, due to their several advantageous characteristics, have recently dominated the data storage industry and its global market. Currently, multi-level cell memories, in which each cell can store more than one bit of data resulting in higher data storage capacities, have gained a considerable amount of research interest. However, this comes at the cost of several limitations and increased performance degradation. Various studies have shown that among several error sources in multi-level cell memories, inter-cell interference is the most significant one. Therefore, to mitigate the devastating effect of the interference, simple, feasible, and yet efficient equalisation techniques become essential for achieving desired data reliability. In this study, first, a thorough analysis on deriving the distribution of the interference-free and interference-affected data is carried out. Then, novel low-complexity equalisation methods are proposed, and their beneficial complexity-performance trade-offs compared with the existing techniques are illustrated. Finally, simulation results are presented to show that the proposed algorithms considerably improve the error performance, while maintaining the low-complexity constraints. [ABSTRACT FROM AUTHOR]

Abstract: Organic resistive memory devices are one of the promising next‐generation data storage technologies which can potentially enable low‐cost printable and flexible memory devices. Despite a substantial development of the field, the mechanism of the resistive switching phenomenon in organic resistive memory devices has not been clearly understood. Here, the time–dependent current behavior of unipolar organic resistive memory devices under a constant voltage stress to investigate the turn‐on process is studied. The turn‐on process is discovered to occur probabilistically through a series of abrupt increases in the current, each of which can be associated with new conducting paths formation. The measured turn‐on time values can be collectively described with the Weibull distribution which reveals the properties of the percolated conducting paths. Both the shape of the network and the current path formation rate are significantly affected by the stress voltage. A general probabilistic nature of the percolated conducting path formation during the turn‐on process is demonstrated among unipolar memory devices made of various materials. The results of this study are also highly relevant for practical operations of the resistive memory devices since the guidelines for time‐widths and magnitudes of voltage pulses required for writing and reading operation can be potentially set. [ABSTRACT FROM AUTHOR]

Phase change memory (PCM) is one of promising technology to replace DRAM with its attractive features such as zero leakage power and high scalability. In PCM, a SET operation needs much more time than a RESET operation. A typical write request concurrently writes 64 bytes to a PCM memory line. Therefore, write latency is mainly determined by SET operations. Previously, PreSET has been proposed to improve PCM performance by exploiting asymmetry in write time. A PreSET operation pro-actively SETs all the bits in the memory line before a dirty cache line is written to PCM. Later, when a write request is processed, only RESET operations are actually performed. Consequently, PreSET reduces write latency and improves system performance. However, such PreSET operations are conducted only at a very coarse-grained level, which reduces the endurance of PCM. Through empirical study, we observe that in most applications the number of dirty words in a dirty line is actually quite limited. If we only SET those dirty words, instead of the whole cache line, we would significantly extend the lifetime of PCM while still achieving desirable performance. Inspired by this observation, we propose a scheme called Partial-PreSET which balances performance and endurance of PCM. The core idea of this scheme is to SET those dirty bits of a cache line in a fine-grained fashion. Our experiments show that the proposed Partial-PreSET scheme significantly improves the average lifetime of PCM system, up to 2.79X, while incurring only 2% system performance loss, compared with the state-of-the-art scheme (i.e., PreSET). [ABSTRACT FROM AUTHOR]

Abstract: The large polydispersity index of functional pendant polymers has hindered their application in semiconductors. Herein, a novel pendant polymer with perylenediimide (PDI) in the side chains was successfully synthesized through ring‐opening metathesis polymerization (ROMP) with a very low polydispersity index. The synthesized polymers were spin‐coated on indium tin oxide (ITO) substrate by using a mixture of 1,2‐dichlorobenzene (o‐DCB) and methanol (MeOH) solvents. The surface morphologies and intermolecular π–π stacking of the fabricated film could be adjusted through tuning of the ratio of o‐DCB and MeOH, and thus, the sandwich‐structured device of ITO/polymer/aluminum exhibited different electrical behavior. The threshold voltages of the devices decreased as the MeOH content was increased from 0 to 30 % (v/v); however, the device changed from being unrewritable to rewritable if the MeOH content was increased to 40 %; a probable mechanism for this process is discussed. It is hoped that this new idea of synthesizing narrow polydispersity index pendant polymers, and the fabrication of high‐quality films through the use of a mixture of solvents could allow high‐performance memory devices to be prepared in the future. [ABSTRACT FROM AUTHOR]

In this paper, we elaborated non-localized drain disturb (DD) in the normally-on silicon-oxide-nitride-oxide‑silicon (SONOS) flash device by experiments and simulations. It was found that a peak value of vertical tunneling oxide (TO) E-Field at channel center occurs along with DD stress time. This indication was ascribed to different charge de-trapping rate at channel-inside and drain-side region. Additionally, the impact of lightly doped drain (LDD) on the DD immunity was fully investigated. It indicated that large dose and high energy of LDD would degrade DD immunity and that LDD optimization achieves better tradeoff between on-current and DD immunity. Finally, this paper confirmed that LDD with larger dose and lower energy is preferable for better tradeoff between on-current and DD immunity. It also reveals that the tradeoff is still inevitable to achieve ultrahigh DD immunity. [ABSTRACT FROM AUTHOR]