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International audience; Graphics Processing Units (GPUs) are over-stressed to accelerate High-Performance Computing applications and are used to accelerate Deep Neural Networks in several domains where they have a life expectancy of many years. These conditions expose the GPUs hardware to (premature) aging, causing permanent faults to arise after the usual end-of-manufacturing test. Techniques to assess the impact of permanent faults in GPUs are then strongly required, thus allowing to estimate the reliability risk and to possibly mitigate it. In this paper, we present a method to evaluate the effects of permanent faults affecting the GPU scheduler and control units, which are the most peculiar and stressed resources, along with the first figures that allow quantifying these effects. We characterize over 5.83x10^5 permanent fault effects in the scheduler and controllers of a gate-level GPU model. Then, we map the observed error categories in software by instrumenting the code of 13 applications and two convolutional neural networks, injecting more than 1.65x10^5 permanent errors. Our two-level fault injection strategy reduces the evaluation time from hundreds of years of gate-level evaluation to hundreds of hours.We found that faults in the GPU parallelism management units can modify the opcode, the addresses, and the status of thread(s) and warp(s). The large majority (up to 99%) of these hardware permanent errors impacts the running software execution. Errors affecting the instruction operation or resource management hang the code, while 45% of errors in the parallelism management or control-flow induce silent data corruptions.

International audience; Timing side-channels are an identified threat for security critical software. Existing countermeasures have a cost either on the hardware requirements or execution time. We focus on low-cost microcontrollers that have a very low computational capacity. Although these processors do not feature out-of-order execution or speculation, they remain vulnerable to timing attacks exploiting the varying latencies of ALU operations or memory accesses. We propose to augment the RISC-V ISA with security primitives that have a guaranteed timing behavior. These primitives allow constant time ALU operations and memory accesses that do not alter the state of the cache. Our approach has a low overhead in terms of hardware cost, binary code size, and execution time both for the constant time secure program and other programs running concurrently on the same hardware.

International audience; In the human brain, learning is continuous, while currently in AI, learning algorithms are pre-trained, making the model non-evolutive and predetermined. However, even in AI models, environment and input data change over time. Thus, there is a need to study continual learning algorithms. In particular, there is a need to investigate how to implement such continual learning algorithms on-chip. In this work, we focus on Oscillatory Neural Networks (ONNs), a neuromorphic computing paradigm performing auto-associative memory tasks, like Hopfield Neural Networks (HNNs). We study the adaptability of the HNN unsupervised learning rules to on-chip learning with ONN. In addition, we propose a first solution to implement unsupervised on-chip learning using a digital ONN design. We show that the architecture enables efficient ONN on-chip learning with Hebbian and Storkey learning rules in hundreds of microseconds for networks with up to 35 fully-connected digital oscillators.

This book lays down the technological foundation for and introduces key artificial intelligence (AI) concepts and technologies for the digitising industry. While this chapter does not exhaustively cover all types of AI, it comprehensively prioritises the features of AI-based industrial applications and designs and defines the reference terminology used in the other chapters of the book. AI integrates several interrelated technologies to solve problems and perform tasks to achieve defined objectives; hence, AI can be approached from many viewpoints, such as mathematics and computer science, linguistics, psychology, neurology, and philosophy. The approach in this chapter is from a technological and industrial perspective, and concepts and functions are presented intuitively and visually, focusing on AI, as it is applied to embedded systems, with industrial automation, interactivity, and sustainability in mind. This already reflects the next-generation deployment of AI into edge devices (called edge AI) and the emergence of different edge layers (i.e., micro-, deep- and meta-edge), which contrasts existing solutions that are currently deployed in the cloud. The edge processing continuum includes sensing, processing and communication devices (micro-edge) close to the physical industrial assets under monitoring, gateways and intelligent controller processing devices (deep-edge) and on-premise multi-use computing devices (meta-edge). Furthermore, instead of attempting to present a definition of AI that is common to all industries, the chapter relies on a framework of classifications and continuums along various dimensions, including the industrial intelligence spectrum, the intelligent capabilities spectrum, the edge-cloud continuum, the symbolic reasoning – pattern recognition continuum and, not the least, the problem-solving spectrum. The chapter introduces some of the main pillars of problem solving, such as expert systems, genetic and evolutionary computation, intelligent agents, machine learning (ML) and more. This chapter, in particular, will detail ML approaches and neural networks. During the past decades, the trends and developments in AI have followed a recurring pattern, where the focus has moved back and forth between logic (symbolic reasoning) and pattern recognition (neural networks), driven by the varying abilities of technologies to acquire data, learn, derive new information and reason to reach decisions. In the last years, machine learning and neural network models have been the primary focus due to advances in hardware development and processing capabilities. Furthermore, embedded machine learning has been increasingly gaining popularity in industrial applications. This chapter introduces several contributions. First, it gives a high-level overview of how AI works. Second, it shows how AI methods and techniques can be incorporated into an industrial design workflow. Finally, it provides a valuable intuitive understanding of how AI methods and techniques work when deployed in edge devices and how they operate in industrial settings.

International audience; Custom hardware accelerators usage is shifting towards new application domains such as graph analytics and unstructured text analysis. These applications expose complex control-flow which is challenging to map to hardware, especially when operating from a C/C++ description using High-Level Synthesis toolchains. Several approaches relying on speculative execution have been proposed to overcome those limitations, but they often fail to handle the multiple interacting speculations required for realistic use-cases. This paper proposes a fully automated hardware synthesis flow based on a source-to-source compiler that identifies and explores intricate speculation configurations to generate speculative hardware accelerators.

International audience; Since several decades, fault tolerance has become a major research field due to transistor shrinking and core number increasing in System-on-Chip (SoC). Especially, faults occurring to Network-on-Chips (NoCs) of those systems have a significant impact, due to the high amount of data, crossing the NoC, for the communication among Intellectual Properties (IPs). Furthermore, existing fault tolerant approaches cannot efficiently deal with several permanent faults, which occur in NoC routers. To address these limitations, we propose the Bit Shuffling meThod (BiSuT) for fault tolerant NoCs that reduces the impact of faults on data communications. To achieve that, the proposed approach exploits, at run-time, the position of permanent faults and changes the order of bits inside a flit. Our method reduces, as much as possible, the impact of faults by transferring the faults on Least Significant Bits (LSBs), instead of keeping them on Most Significant Bits (MSBs). The results obtained by extensive evaluations show that BiSuT can reduce the impact of multiple permanent faults, with low hardware costs, compared to existing approaches, like Hamming code.

International audience; Emerging nonvolatile memory technologies are attracting interest from the system design level to implement alternatives to conventional von-Neumann computing architectures. In particular, the hafnium oxide-based ferroelectric (FE) memory technology is fully CMOS-compatible and has already been used for logic-in-memory architectures or compact ternary content addressable memory (TCAM) cells. These enable the tight combination of different functionalities in the same circuit to reduce implementation area and energy consumption. In this article, we propose a new hybrid memory circuit that combines TCAM and normal memory capability: the Ternary Content addressable and MEMory (TC-MEM). A 1-bit TC-MEM circuit is proposed and discussed in detail, both as a concept and through its implementation in a 28-nm ferroelectric field-effect transistor (FeFET) technology. Measurement results demonstrate the circuit functionality. We also discuss how to scale it to multibit circuits, as well as its use both as a TCAM and as a normal memory allowing the implementation of reversible functions using one memory table instead of two memory tables, and in-memory-computing concepts.

International audience; The adoption of In-Memory Computing (IMC) architectures is one of the promising approaches to efficiently solve the Von Neumann bottleneck problem. In addition to arithmetic operations, IMC architectures aim at integrating additional logic operations directly in the memory array or/and at the periphery for saving time and power consumption. In this paper, a comprehensive model of a 128x128 bitcell array based on a 28nm FD-SOI process technology has been considered to analyze the behavior of IMC 8T SRAM bitcells in the presence of resistive-open defects injected in the read port. A hierarchical analysis including a detailed study of each defect was performed in order to determine their impact both in memory and computing modes, both locally on the defective bitcell and globally on the array. Experimental results show that the IMC mode offers the most effective detectability of resistive-open defects.

International audience; Precision Beekeeping is a subfield of Precision Agriculture. It collects data on colonies of bees using sensors to assist beekeepers and preserve bees. The existing solutions include collecting voluminous data, such as images and sound, from up close or inside a beehive. The collection, transfer, and processing of such data are energy-intensive processes. However, most Precision Beekeeping systems work under a limited energy budget. Thus, such systems must take this constraint into account. This article focuses on the placement of energy-aware Precision Beekeeping services at the edge and in the cloud. We deploy a set of smart beehives in order to conduct experiments and collect real data. Then, we simulate large-scale systems with embedded services to add more realism to the experimental study. Our results show that parameters like the number of smart beehives, the frequency of data collection, and the characteristics of the cloud server impact the placement of these services to enhance energy efficiency.

International audience; Fault injection attacks represent an effective threatto embedded systems. Recently, Laurent et al. have reported thatfault injection attacks can leverage faults inside the microarchi-tecture. However, state-of-the-art counter-measures, hardware-only or with hardware support, do not consider the integrityof microarchitecture control signals that are the target of thesefaults.We present MAFIA, a microarchitecture protection againstfault injection attacks. MAFIA ensures integrity of pipelinecontrol signals through a signature-based mechanism, and en-sures fine-grained control-flow integrity with a complete indirectbranch support and code authenticity. We analyse the securityproperties of two different implementations with different secu-rity/overhead trade-offs: one with a CBC-MAC/Prince signaturefunction, and another one with a CRC32. We present ourimplementation of MAFIA in a RISC-V processor, supportedby a dedicated compiler toolchain based on LLVM/Clang. Wereport a hardware area overhead of 23.8 % and 6.5 % for theCBC-MAC/Prince and CRC32 respectively. The average code sizeand execution time overheads are 29.4 % and 18.4 % respectivelyfor the CRC32 implementation and are 50 % and 39 % for theCBC-MAC/Prince.

International audience; This work introduces an Open-Source, High-Performance, Out-of-Order (OoO), L1 Data Cache (HPDcache) compatible with RISC-V processor cores.As a case-study, this HPDcache was successfully integrated with the CVA6 core.A silicon implementation is being tapeout in the context of the European Processor Initiative (EPI) project and further improvements will be made on the context of the KDT Tristan project.The HPDcache SystemVerilog Register-Transfer Level (RTL) sources are contributed as open-source with permissive Solderpad v2.1 license. It is available through the OpenHW Github.

International audience; Deep Neural Networks (DNNs) show promising performance in several application domains. Nevertheless, DNN results may be incorrect, not only because of the network intrinsic inaccuracy, but also due to faults affecting the hardware. Ensuring the fault tolerance of DNN is crucial, but common fault tolerance approaches are not cost-effective, due to the prohibitive overheads for large DNNs. This work proposes a comprehensive framework to assess the fault tolerance of DNN parameters and cost- effectively protect them. As a first step, the proposed framework performs a statistical fault injection. The results are used in the second step with classification-based machine learning methods to obtain a bit-accurate prediction of the criticality of all network parameters. Last, Error Correction Codes (ECCs) are selectively inserted to protect only the critical parameters, hence entailing low cost. Thanks to the proposed framework, we explored and protected two Convolutional Neural Networks (CNNs), each with four different data encoding. The results show that it is possible to protect the critical network parameters with selective ECCs while saving up to 79% memory w.r.t. conventional ECC approaches.

International audience; Dans les études archéozoologiques, la mise en place d'approches classiques (attribution anatomique et taxinomique, taphonomie) combinées à des analyses tracéologiques et/ou biomoléculaires (paléoprotéomique) est un des moyens actuellement développé pour appréhender les comportements des néandertaliens et leur exploitation du matériel faunique.Le site de Biache-Saint-Vaast (BSV, Pas-de-Calais, MIS 7) a livré 3 niveaux riches en restes osseux de grands mammifères terrestres. Dans ces assemblages, ont été identifié des vestiges comportant des plages de marques en creux, apparentées à des stigmates de percussion sur du matériel lithique. Avec plus de 300 restes de ce type actuellement identifiés, BSV constitue l'un des assemblages les plus importants connu, avec une préservation exceptionnelle pour un site de plein air, soulevant de nombreuses problématiques quant à l'utilisation des restes fauniques comme outils par les populations néandertaliennes. Y-a-t-il une intentionnalité dans le choix de la matière première utilisée ? Existe-t-il une préparation particulière de l'os ? Est-il possible de mettre en évidence des comportements particuliers relatifs à la « fabrication » de tels outils ?L'étude détaillée, suivant des approches multi-proxy, de restes osseux comprenant des plages à impression, appelés « retouchoirs », est encore peu développée. La bonne préservation des ossements à BSV octroie la mise en place de ces analyses. Les études archéozoologiques, taphonomiques et tracéologiques, non-invasives, sont employées pour comprendre l'acquisition et l'utilisation du vestige. Les analyses protéomiques, permettent de pallier aux limites des attribution taxinomiques classiques et d'employer des techniques peu invasives. Les protéines se détériorant moins rapidement que l'ADN elles sont par ailleurs applicables sur un grand nombre de restes. Cette combinaison d'études a pour but de mieux comprendre la conception (utilisation préférentielle d'un taxon, potentielle préparation des supports osseux, etc.) et l'utilisation de ce type de matériel.Les premiers résultats obtenus semblent indiquer que les restes des trois espèces les plus représentées dans le cortège faunique identifié à BSV ont été employés comme « retouchoirs » : l'aurochs (Bos primigenius), l'ours brun (Ursus arctos) et le rhinocéros des prairies (Stephanorhinus hemitoechus), avec une utilisation quasi-exclusive pour la percussion d'outils lithiques pour les pièces analysées, et également leur emploi lors de la phase de ‘fabrication'. Ces résultats démontrent l'intérêt de l'application conjointe de différentes approches et méthodes pour les connaissances de l'utilisation de ce type d'outil en os et plus généralement de la gestion de la faune de grands herbivores par les populations néandertaliennes. Des analyses sur un plus large spectre de restes osseux tenteront de caractériser l'ensemble de l'assemblage de Biache-Saint-Vaast et de le mettre en relation avec d'autres gisements de la région.

The design of heterogeneous system-on-chip platforms is complex with many possible combinations. Detailed simulation of different solutions is necessary to determine the best design. Existing simulation environments (such as gem5) are limited as they are purely software based and do not take into account heterogeneous architectures. To address these limitations, the use of reprogrammable FPGA components to accelerate simulation is motivated. Our work is divided into two parts. The first part is experimental and studied an approach to design heterogeneous architectures focusing on simulating performance models of architecture components (hardware accelerators and processor cores) on FPGA. The second part is methodological and concerns a flow to determine the best microarchitecture in terms of performance to energy consumption ratio. This flow combines a software architecture simulator and a hyperparameter optimization method to find the best combination of parallelism, loop unrolling strategies, and memory interfaces. Experiments were conducted on different problems to determine the most optimal solutions in terms of energy efficiency.; La conception de plates-formes de système sur puce hétérogènes est complexe avec de nombreuses combinaisons possibles. La simulation détaillée de différentes solutions est nécessaire pour déterminer le meilleur design. Les environnements de simulation existants (tels que gem5) sont limités car purement logiciels et ne prennent pas en compte les architectures hétérogènes. Pour pallier ces limitations, l'utilisation de composants reprogrammables FPGA pour accélérer la simulation est motivée. Notre travail est divisé en deux parties. La première partie est d'ordre expérimental et a étudié une approche de conception d'architectures hétérogènes en se concentrant sur la simulation de modèles de performance de composants de l'architecture (accélérateurs matériels et cœurs de processeurs) sur FPGA. La seconde partie est méthodologique et concerne un flot pour déterminer la meilleure microarchitecture en termes de rapport performance/consommation d'énergie. Ce flot combine un simulateur logiciel d'architecture et une méthode d'optimisation d'hyperparamètres pour trouver la meilleure combinaison de parallélisme, stratégies de déroulage de boucles et interfaces de mémoire. Les expérimentations ont été menées sur différents problèmes pour déterminer les solutions les plus optimales en termes d'efficacité énergétique.

Motion capture is traditionally performed with marker-based systems. However, these solutions are hardly compatible with on-field sports analysis, and markerless alternatives are being explored. One of the most promising prospects lies at the intersection of machine learning for 2D pose estimation, computer vision for 3D reconstruction from multiple video sources, and biomechanics for constraining 3D coordinates to an anatomically consistent model. We released Pose2Sim, an open-source package striving to answer these needs in a user-friendly way. OpenPose 2D keypoint coordinates are robustly triangulated, and serve as input for a full-body OpenSim inverse kinematics procedure. Pose2Sim robustness has been evaluated for people entering and exiting the field of view, degraded image quality, calibration errors, and decreased number of cameras. Its accuracy has also been assessed and deemed sufficient for walking, running, and ergometer cycling analysis. In the context of a competition, using lightweight and wireless action cameras is convenient. We tested such hardware on boxing sequences and proposed post-calibration and post-synchronization procedures. Finally, capturing both the athlete and their equipment can be valuable. We studied the kinematics of both a pilot and his bike in a BMX race by training a DeepLabCut bike model, triangulated and mapped on a custom-articulated OpenSim model. This work brings out interesting new perspectives for the analysis of sports movement.; La capture de mouvement est traditionnellement effectuée à l’aide de marqueurs réfléchissants placés sur la peau. Cependant, ces méthodes ne conviennent pas à l'analyse contextuelle du sport sur le terrain, et des alternatives sans marqueur sont étudiées. L’une des perspectives les plus prometteuses à ce sujet se situe à l’intersection de l’apprentissage machine pour l’estimation de pose 2D, de la vision par ordinateur pour la reconstruction 3D à partir de plusieurs sources vidéo, et de la biomécanique pour contraindre les coordonnées 3D à un modèle anatomiquement cohérent. Nous avons proposé Pose2Sim, un package open-source et simple d’utilisation visant à répondre à ces besoins. Les détections 2D d’OpenPose sont triangulées de manière robuste, et transmises à OpenSim pour une cinématique inverse corps complet. La robustesse de Pose2Sim a été estimée face à des personnes "parasites" entrant le champ de vision, à une qualité d’image dégradée, à des erreurs de calibration, et à un nombre de caméras réduit. Son exactitude a également été évaluée, et jugée satisfaisante pour l’analyse de la marche, de la course, et du cyclisme. Dans un contexte de compétition, il peut être utile d'employer des caméras légères et sans fil de type GoPro. Nous avons testé ce matériel sur des séquences de boxe, et proposé des procédures de post-calibration et de post-synchronisation. Enfin, capturer à la fois l’athlète et son équipement serait intéressant. Nous avons calculé la cinématique d’un pilote de BMX avec son vélo, en entraînant un modèle DeepLabCut pour le vélo, triangulé et appliqué sur un modèle poly-articulé OpenSim. L’ensemble de ces résultats apporte des perspectives novatrices pour l’analyse du mouvement sportif.

International audience; A fundamental step in circuit design is the placement of pipeline stages, which can drastically increase the data throughput. Retiming allows optimizing the pipeline with regard to a criterion, for example the required number of registers. This article presents an extension of Timed Petri Net to model synchronous electronic circuits, in order to explore the design space of pipelines. The Timed Petri Nets “à la Ramchandani” with a maximal step firing rule, have notably been used for the modeling of electronic circuits. The RTPN extension, through the reset which model the pipeline stages, and through the delayable transitions which relax some temporal constraints, makes it possible to widen the design space of pipelined systems, and thus to deal with both the retiming and the verification. After a formal definition of this model, we present a method to explore pipelines verifying temporal properties. We apply our approach to a time-multiplexing property allowing the mutualization of operators while minimizing the number of registers.

This paper presents a new solution to address the challenge of increasing memory usage in high-performance computing simulations of Lattice-Bolzmann or Finite-Volume schemes.Our approach utilises a lossy compression scheme based on the Discrete Wavelet Transform (DWT) to achieve high compression ratios while preserving the accuracy of the simulation.Our evaluation on two different FV/LBM schemes demonstrates that the approach can reduce memory usage by several orders of magnitude.; Ce papier présente une nouvelle solution pour faire face à l'augmentation de l'utilisation de la mémoire dans les simulations haute performance basées sur les méthodes Lattice-Bolzmann ou Volumes Finis.Notre approche utilise un schéma de compression avec perte basé sur la transformée par ondelettes discrète (DWT) pour obtenir des taux de compression élevés tout en préservant la précision de la simulation.Notre évaluation sur deux différents schémas VF/LBM démontre que l'approche peut réduire l'utilisation de la mémoire de plusieurs ordres de grandeur.

Digital electronics based on von Neumann's architecture are reaching their limits to solve large scale problems essentially due to the memory fetching. Instead, recent efforts to bring the memory near the computation have enabled highly parallel computations at low energy cost. Oscillatory Neural Network (ONN) is one example of in-memory analog computing paradigm consisting of coupled oscillating neurons. When implemented in hardware, ONNs naturally perform gradient descent of an energy landscape that makes them particularly suited for solving optimization problems. Although the ONN computational capability and its link with the Ising model are known for decades, implementing a large-scale ONN remains difficult. Beyond the oscillators' variations, there are still design challenges such as having compact, programmable synapses and a modular architecture for solving large problem instances.In this paper, we propose a mixed-signal architecture named Saturated Kuramoto ONN (SKONN) that leverages both analog and digital domains for efficient ONN hardware implementation. SKONN computes in the analog phase domain while propagating the information digitally to facilitate scaling up the ONN size. SKONN's separation between computation and propagation enhances the robustness and enables a feed-forward phase propagation that is showcased for the first time. Moreover, the SKONN architecture leads to unique binarizing dynamics that are particularly suitable for solving NP-hard combinatorial optimization problems such as finding the Weighted Max-cut of a graph. We find that SKONN's accuracy is as good as the Goemans-Williamson 0.878-approximation algorithm for Max-cut; whereas SKONN's computation time only grows logarithmically. We report on Weighted Max-cut experiments using a 9-neuron SKONN proof-of-concept on PCB. Finally, we present a low-power 16-neuron SKONN integrated circuit and illustrate SKONN's feed-forward ability while computing the XOR function.

Multiple Constant Multiplication (MCM) is a ubiquitous problem for numerous computation-intensive applications. A standard and efficient approach is to replace generic multipliers by multiplierless architectures based on bit-shifts and additions. The adder graphs describing the multiplierless circuits can be optimized according to various metrics, in particular improving throughput by pipelining. In this paper, we improve the state-ofthe-art for the design of pipelined adder graphs by searching for an optimal solution directly from target coefficients. In contrast to existing approaches, which are based on fixed adder graphs or heuristics, our solution is to describe the complete design space with Mixed-Integer Linear Programming (MILP). This results in an optimization model that can be solved to find optimal adder graphs and prove the optimality of the solutions thanks to the efficiency of modern MILP solvers. Mathematical modeling allows for an easily extendable tool which can target FPGAs and ASICs and adapt to evolving hardware models/metrics. With this work, we provide a modular framework to automate the design of adder graph-based circuits with exact optimization. The experiments demonstrate efficiency of our approach which fuses multiple design steps into a single problem.

National audience

The field of neuromorphic computing has been rapidly evolving in recent years, with an increasing focus on hardware design and reliability. This special session paper provides an overview of the recent developments in neuromorphic computing, focusing on hardware design and reliability. We first review the traditional CMOS-based approaches to neuromorphic hardware design and identify the challenges related to scalability, latency, and power consumption. We then investigate alternative approaches based on emerging technologies, specifically integrated photonics approaches within the NEUROPULS project. Finally, we examine the impact of device variability and aging on the reliability of neuromorphic hardware and present techniques for mitigating these effects. This review is intended to serve as a valuable resource for researchers and practitioners in neuromorphic computing., Comment: 10 pages, 4 figures, 4 tables

In areas of activity where the notion of accountability is strong, the adoption of artificial intelligence (AI) is limited by the opacity and lack of understanding of its behavior, all the more so in the embedded domain where neural networks are compressed and executed on microcontrollers. While the NIST introduced in 2021 several principles allowing the AI explainability, this paper introduces a novel scheme, HistoTrust, combining secure hardware and blockchain technology to bring trust in the traceability of AI behavior and allow its explainability. HistoTrust attests in an Ethereum ledger all the relevant data produced by a physical device, especially the heuristics inferred by AI. Thus, the audition of the ledger allows security verifications and AI behavior analysis.

International audience; Multiple Constant Multiplication (MCM) over integers is a frequent operation arising in embedded systems that require highly optimized hardware. An efficient way is to replace costly generic multiplication by bit-shifts and additions, i. e. a multiplierless circuit. In this work, we improve the state-ofthe-art optimal approach for MCM, based on Integer Linear Programming (ILP). We introduce a new lower-level hardware cost, based on counting the number of one-bit adders and demonstrate that it is strongly correlated with the LUT count. This new model for the multiplierless MCM circuits permitted us to consider intermediate truncations that permit to significantly save resources when a full output precision is not required. We incorporate the error propagation rules into our ILP model to guarantee a user-given error bound on the MCM results. The proposed ILP models for multiple flavors of MCM are implemented as an open-source tool and, combined with the FloPoCo code generator, provide a complete coefficient-to-VHDL flow. We evaluate our models in extensive experiments, and propose an in-depth analysis of the impact that design metrics have on actually synthesized hardware.

NISQ devices have several physical limitations and unavoidable noisy quantum operations, and only small circuits can be executed on a quantum machine to get reliable results. This leads to the quantum hardware under-utilization issue. Here, we address this problem and improve the quantum hardware throughput by proposing a Quantum Multi-programming Compiler (QuMC) to execute multiple quantum circuits on quantum hardware simultaneously. This approach can also reduce the total runtime of circuits. We first introduce a parallelism manager to select an appropriate number of circuits to be executed at the same time. Second, we present two different qubit partitioning algorithms to allocate reliable partitions to multiple circuits – a greedy and a heuristic. Third, we use the Simultaneous Randomized Benchmarking protocol to characterize the crosstalk properties and consider them in the qubit partition process to avoid the crosstalk effect during simultaneous executions. Finally, we enhance the mapping transition algorithm to make circuits executable on hardware using a decreased number of inserted gates. We demonstrate the performance of our QuMC approach by executing circuits of different sizes on IBM quantum hardware simultaneously. We also investigate this method on VQE algorithm to reduce its overhead.

Over the years, System-on-Chip (SoC) has evolved from a single processor in a chip to multi/many processors in chips containing billions of transistors. With the evolution of SoC, new research topics have risen on interconnect between processors in a chip. Network-on-Chip(NoC) has been proposed as a solution for more dynamic communication links to connect large number of Intellectual Property (IP)s. Secondly, to overcome drawbacks of electrical NoC, Optical communication link has been proposed as a promissing solution. This type of NoC provides low latency and high bandwith, but it suffers from low power efficiency. In this thesis, we address this topic and we aim to develop techniques to manage laser power consumption. To address this challenge, we exploit the approximation concept and we apply it to the ONoC to propose two types of communications: Approximate and accurate communications. Our proposal is applied to Floating-Point (FP) numbers by using low-power optical signals for LSB, at the cost of higher error rate. These approximate optical signals allow a drastic reduction in the laser power consumption. In parallel, to ensure the communication accuracy on MSBs, the laser power levels are remained using high power signals. Simulations results demonstrate that a reduction of to 42% of laser power can be obtained for Streamcluster application with a limited degradation at the application level. Furthermore, we propose to manage the communications accordong to the distance between source and destination cores. However, this fine-grain distance-aware management could be too costly, so we propose a low overhead distance-aware technique based on only two distances Short/Long classes. The results of our evaluation show drastic laser power reduction of 20%for example for Streamcluster application.; Depuis leur apparition, le système sur puce (SoC) a évolué d'un processeur unique dans une puce à plusieurs processeurs dans des puces contenant des milliards de transistors. Avec l'évolution des SoC, de nouveaux sujets de recherche ont vu le jour sur l'interconnexion entre les processeurs d'une puce. Le réseau sur puce (NoC) a été proposé comme solution pour des liaisons de communication plus dynamiques afin de connecter un grand nombre de propriétés intellectuelles (IP). Deuxièmement, pour surmonter les inconvénients du NoC électrique, une liaison de communication optique a été proposée comme solution prometteuse. Ce type de NoC offre une faible latence et une bande passante élevée, mais il souffre d'une faible efficacité énergétique. Dans cette thèse, nous abordons ce sujet et nous visons à développer des techniques pour gérer la consommation d'énergie des lasers. Pour relever ce défi, nous exploitons le concept d'approximation et nous l'appliquons à l'ONoC pour proposer deux types de communications : des communications approximatives et précises. Notre proposition est appliquée aux nombres à virgule flottante (FP) en utilisant des signaux optiques de faible puissance pour LSB, au prix d'un taux d'erreur plus élevé. Ces signaux optiques approximatifs permettent une réduction drastique de la consommation d'énergie du laser. En parallèle, pour assurer la précision de la communication sur les MSB, les niveaux de puissance laser sont maintenus en utilisant des signaux de haute puissance. Les résultats des simulations démontrent qu'une réduction de 42 % de la puissance laser peut être obtenue pour l'application Streamcluster avec une dégradation limitée au niveau de l'application. De plus, nous proposons de gérer les communications en fonction de la distance entre les cœurs source et destination. Cependant, cette gestion sensible à la distance à grain fin pourrait être trop coûteuse, nous proposons donc une technique sensible à la distance à faible surcoût basée sur seulement deux classes de distances Court/Long. Les résultats de notre évaluation montrent une réduction drastique de la puissance laser de 20 %, par exemple pour l'application Streamcluster.

Today computing centric von Neumann architectures face strong limitations in the data-intensive context of numerous applications. The key limitation is the memory wall due to increased performance gap between processors and memories. To mitigate this gap, cache hierarchy was introduced but it largely increased energy consumption while not being adapted for modern big datasets. Not only those architectures struggle with big datasets due to their high energy consumption and slow bandwidth, they can no longer be improved through technological advances such as node scaling. This calls for a paradigm shift to data centric architecture where treating massive amounts of data in a parallel fashion is the core principle.New emerging Non-Volatile Memories (NVM) promise high density data storage and can easily integrate In-Memory Computing (IMC). IMC purposes is to compute where the data is or the closest to, to suppress back and forth data movements from the memory to the cores. Existing solutions use analog computing that has high efficiency but limited flexibility. When data needs to be written back after computation, endurance of NVM is often not discussed. We design a digital wrapper that extends memory functionality with vector computing capabilities and develop a simulation platform for architecture exploration. Our digital wrapper, aka C-SRAM, can be inte- grated with most memory technologies and comes with its own small SRAM buffer. We demonstrate that computing at the top of the memory hierarchy, i.e. close to the permanent storage, grants in average 17.4× energy reduction and 12.9× speed-up versus SIMD baseline. Thanks to SRAM buffer, NVM’s endurance is not impaired and thereby extends system lifetime compared to other IMC solutions.; Les architectures d’aujourd’hui sont basées sur le modèle de von Neumann qui place au centre l’exécution des instructions. Ces architectures font face à de fortes limitations dans le contexte du big data. En effet, le mur mémoire est un phénomène lié à l’écart grandissant de performances entre les processeurs et les mémoires depuis les années 80. Pour atténuer cet écart, une hiérarchie de caches a été mise en place mais elle a en contrepartie largement augmentée la consommation énergétique sans être adaptée pour les grands jeux de données modernes. Non seulement ces architectures ont du mal avec une masse de données toujours croissantes à cause de leur haute consommation énergétique et leur faible débit, elles ne peuvent plus uniquement se baser sur les avancées technologiques pour s’améliorer. Ceci appelle à un changement de paradigme vers des architectures data centrées où le traitement de quantités de données massives en parallèle est le principe de base. De nouvelles mémoires non volatiles promettent du stockage haute densité et peuvent intégrer du calcul en mémoire. L’intérêt de calculer en mémoire est d’opérer là où se trouve la donnée, ou tout du moins le plus proche possible, pour supprimer les allées et venues permanentes entre la mémoire et les cœurs de calcul. Les solutions existantes utilisent du calcul analogique très efficace mais prompt au bruit et avec une flexibilité limitée. Quand les données doivent être réécrites en mémoire, l’endurance de ces mémoires non volatiles n’est pas discutée. Nous concevons un emballage numérique qui étend les fonctionnalités mémoire avec du calcul vectoriel et développons une plateforme de simulation pour faire de l’exploration architecturale. Notre circuit, bien nommé C-SRAM, peut être intégré avec la plupart des technologies mémoire et est équipé de sa propre mémoire SRAM. Nous démontrons qu’effectuer le calcul au sommet de la hiérarchie mémoire, c’est à dire proche du stockage permanent, permet une réduction de la consommation énergétique d’un facteur 17.4 et une accélération du traitement en moyenne d’un facteur 12.9 comparé à un traitement avec un cœur SIMD. Grâce à la mémoire tampon intégrée, l’endurance de la mémoire non volatile n’est pas impactée et de fait, l’espérance de vie du système s’en trouve augmentée par rapport à d’autres solutions de calcul en mémoire.

International audience; This paper proposes a new microarchitectural scheme for reducing the hardware complexity of the integer register file of a superscalar processor. The register file is split into two banks holding even-numbered and odd-numbered physical registers, respectively. Each bank provides one read port to each two-input integer execution unit. This way, each bank has half the total number of read ports, and the register file area is roughly halved, which reduces the energy dissipated per register access and the register access time. However, a bank conflict occurs when both inputs of a two-input micro-operation lie in the same bank. Bank conflicts hurt performance and we propose a simple solution to remove most bank conflicts, thus recovering most of the lost performance.

International audience; The energy consumption of manycore architectures is dominated by data movement, which calls for energy-efficient and high-bandwidth interconnects. To overcome the bandwidth limitation of electrical interconnects, integrated optics appear as a promising technology. However, it suffers from high power overhead related to low laser efficiency, which calls for the use of techniques and methods to improve its energy costs. Besides, approximate computing is emerging as an efficient method to reduce energy consumption and improve execution speed of embedded computing systems. It relies on allowing accuracy reduction on data at the cost of tolerable application output error. In this context, the work presented in this article exploits both features by defining approximate communications for error-tolerant applications. We propose a method to design realistic and scalable nanophotonic interconnect supporting approximate data transmission and power adaption according to the communication distance to improve the energy efficiency. For this purpose, the data can be sent by mixing low optical power signal and truncation for the Least Significant Bits (LSB) of the floating-point numbers, while the overall power is adapted according to the communication distance. We define two ranges of communications, short and long, which require only four power levels. This reduces area and power overhead to control the laser output power. A transmission model allows estimating the laser power according to the targeted BER and the number of truncated bits, while the optical network interface allows configuring, at runtime, the number of approximated and truncated bits and the laser output powers. We explore the energy efficiency provided by each communication scheme, and we investigate the error resilience of the benchmarks over several approximation and truncation schemes. The simulation results of ApproxBench applications show that, compared to an interconnect involving only robust communications, approximations in the optical transmission led to up to 53% laser power reduction with a limited degradation at the application level with less than 9% of output error. Finally, we show that our solution is scalable and leads to 10% reduction in the total energy consumption, 35× reduction in the laser driver size, and 10× reduction in the laser controller compared to state-of-the-art solution.

International audience; The design of glitch-resistant higher-order masking schemes is an important challenge in cryptographic engineering. A recent work by Moos et al. (CHES 2019) showed that most published schemes (and all efficient ones) exhibit local or composability flaws at high security orders, leaving a critical gap in the literature on hardware masking. In this paper, we first extend the simulatability framework of Belaïd et al. (EUROCRYPT 2016) and prove that a compositional strategy that is correct without glitches remains valid with glitches. We then use this extended framework to prove the first masked gadgets that enable trivial composition with glitches at arbitrary orders. We show that the resulting "Hardware Private Circuits" approach the implementation efficiency of previous (flawed) schemes. We finally investigate how trivial composition can serve as a basis for a tool that allows verifying full masked hardware implementations (e.g., of complete block ciphers) at any security order from their HDL code. As side products, we improve the randomness complexity of the best published refreshing gadgets, show that some S-box representations allow latency reductions and confirm practical claims based on implementation results.

International audience; One of the main challenges of wireless sensor networks is to maintain sensor nodes alive as long as possible, and a lot of efforts are dedicated to enable energy efficient communications. Wake-Up Receivers (WuRs) represent a promising solution for reducing the power consumption of nodes by enabling asynchronous communications. However, to achieve an ultra-low power consumption, WuRs circuits are kept as simple as possible, inducing a low sensitivity and thus a short range communication. As channel coding improves sensitivity, we propose to take advantage of the computing capability of the WuRs to apply a specific channel coding. The novelty resides in applying Minimum Energy coding with an Early Shutdown (MEES) of WuRs based on On-Off Keying (OOK) detectors. Both theoretical derivations and Monte-Carlo simulations show that the proposed coding scheme improves the reliability. Moreover, Moreover, MEES has been implemented on a non-coherent WuR prototype, and it is shown through experimentation that WuR reliability can be raised up to 22% compared to uncoded communications. Moreover, both the energy consumption and the latency can be significantly decreased thanks to the shutdown mechanism of MEES.

· Print ISSN: 1943-0663· Online ISSN: 1943-0671; International audience; Driver drowsiness is one of the major causes of accidents and fatal road crashes, causing a high human andeconomic cost. Recently, automatic drowsiness detection has begun to be recognized as a promising solution, receiving growing attention from industry and academics. In this letter, we propose to embed a convolutional neural network (CNN)-based solution in smart connected glasses to detect eye blinks and use them to estimate the driver’s drowsiness level. This innovative solution is compared with a more traditional method, based on a detectionthreshold mechanism. The performance, battery lifetime and memory footprint of both solutions are assessed for embedded implementation in connected glasses. The results demonstrate that CNN outperforms the accuracy obtained by the thresholdbased algorithm by more than 7%. Moreover, increased overheads in terms of memory and battery lifetime are acceptable, thus making CNN a viable solution for drowsiness detection in wearable devices.

Embedded systems are ubiquitous in our everyday life. Those embedded systems, by their nomadic nature, are particularly sensitive to the so-called fault injection attacks. For example, an attacker might inject a physical perturbation in an integrated circuit to compromise the security features of the system. Originally used to compromise cryptographic systems, those attacks can now target any kind of system. Notably, those attacks enable to compromise the execution of a program. In this manuscript, we introduce a new security property to protect the execution of instructions in the microarchitecture: execution integrity. From this property, we describe the concept of SCI-FI, a counter-measure that ensures the protection of the whole instruction path thanks to code, control-flow and execution integrity properties. We build SCI-FI around a bit vector that we call pipeline state and that is composed of microarchitecture control signals. Two modules interact around the pipeline state to ensure the security properties. The first module computes a signature from the pipeline state to ensure code and control-flow integrity and partially execution integrity. The second module completes the execution integrity support in the microarchitecture thanks to a redundancy mechanism. We also propose a solution for indirect branches and interrupts that are required to design embedded systems. We implement two versions of SCI-FI, one built around a cryptographic primitive which provides the best security level and another lighter one built around a CRC to maximize the performances. We integrate SCI-FI into a 32 bits RISC-V processor, and we modify the LLVM compiler. We analyze the security provided by our two implementations and we show that SCI-FI, even with the lightweight implementation, is robust against state-of-the-art attacker. Finally, we evaluate the performances of our implementations through an ASIC synthesis and through the execution of the benchmark suite Embench-IoT. We show that SCI-FI has comparable performances to state-of-the-art counter-measures while ensuring a new security property: execution integrity.; Les systèmes embarqués numériques sont omniprésents dans notre environnement quotidien. Ces systèmes embarqués, par leur caractère nomade, sont particulièrement sensibles aux attaques dites par injection de fautes. Par exemple, un attaquant peut injecter une perturbation physique dans un circuit électronique pour compromettre les fonctionnalités de sécurité du système. Originellement utilisées pour compromettre des systèmes cryptographiques, ces attaques permettent aujourd'hui de cibler n'importe quel type de système. Ces attaques permettent notamment de compromettre l'exécution d'un programme. Dans ce manuscrit, nous introduisons une nouvelle propriété de sécurité pour protéger l'exécution des instructions dans la microarchitecture: l'intégrité d'exécution. À partir de cette propriété, nous décrivons le concept de SCI-FI, une contre-mesure qui assure la protection de l'intégralité du chemin d'instructions en assurant l'intégrité du code, du flot de contrôle et d'exécution. Pour cela, nous construisons un vecteur de bits que nous appelons pipeline state à partir de signaux de contrôle dans la microarchitecture. À partir du pipeline state, deux modules s'articulent pour assurer les propriétés de sécurité. Le premier module calcule une signature à partir du pipeline state assurant ainsi l'intégrité du code, du flot de contrôle et une partie de l'intégrité d'exécution. Le second module complète l'intégrité d'exécution dans la microarchitecture en utilisant un mécanisme de redondance. Nous proposons également le support et la sécurisation des branchements indirects et des interruptions, nécessaires pour la conception de systèmes embarqués. Nous réalisons deux imPlémentations de SCI-FI, l'une construite sur une primitive cryptographique assurant un niveau de sécurité maximal et l'autre plus légère construite sur une fonction CRC privilégiant les performances. Pour cela, nous intégrons SCI-FI dans un processeur RISC-V 32 bits et modifions la chaîne de compilation LLVM. Nous réalisons une analyse de sécurité des différents éléments qui composent SCI-FI dans chaque implémentation. Nous montrons ainsi que SCI-FI, même avec l'implémentation privilégiant les performances, est robuste face à un attaquant disposant de moyens d'injection de fautes à l'état de l'art. Enfin, nous évaluons les performances de nos implémentations par une synthèse dans un flot de conception ASIC et par l'exécution en simulation de la suite de test Embench-IOT. Nous montrons ainsi que SCI-FI a des performances équivalentes aux contre-mesures de l'état de l'art tout en assurant une propriété de sécurité supplémentaire, l'intégrité d'exécution.

International audience; The reliability evaluation of Deep Neural Networks (DNNs) executed on Graphic Processing Units (GPUs) is a challenging problem since the hardware architecture is highly complex and the software frameworks are composed of many layers of abstraction. While software-level fault injection is a common and fast way to evaluate the reliability of complex applications, it may produce unrealistic results since it has limited access to the hardware resources and the adopted fault models may be too naive (i.e., single and double bit flip). Contrarily, physical fault injection with neutron beam provides realistic error rates but lacks fault propagation visibility. This paper proposes a characterization of the DNN fault model combining both neutron beam experiments and fault injection at software level. We exposed GPUs running General Matrix Multiplication (GEMM) and DNNs to beam neutrons to measure their error rate. On DNNs, we observe that the percentage of critical errors can be up to 61%, and show that ECC is ineffective in reducing critical errors. We then performed a complementary software-level fault injection, using fault models derived from RTL simulations. Our results show that by injecting complex fault models, the YOLOv3 misdetection rate is validated to be very close to the rate measured with beam experiments, which is 8.66× higher than the one measured with fault injection using only single-bit flips.

This document presents my research activities since my recruitment at the University of Nantes in September 2004. These activities were successively carried out within the IREENA laboratory (Institute for Research in Electronics and Electrotechnics of Nantes Atlantique) until 2012, then within the IETR laboratory (Institute of Electronics and Digital Technologies). The scope of these activities corresponds to the design of hardware and software architectures of embedded electronic systems. In this context, my research activities have focused on the definition of methods favouring the modelling and simulation of hardware and software architectures in order to optimize them under time, cost and energy constraints.In this document, during the presentation of each of the covered topics, I report on the framework of this work, the nature of the contributions made and the approach undertaken. In doing so, I also explain my role in the supervision of the students who participated and contributed to this work and more broadly the collaborations set up. This synthesis tries to reconcile clarity and precision of the explanations. This document has three main parts. The first part corresponds to a detailed CV, summarizing in particular my professional experience with regard to the various activities carried out in research and teaching. The second part details in five chapters the research activities carried out since obtaining the doctoral degree, retracing the most significant results. Finally, the third part presents an assessment of the activities carried out and establishes a potential research program taking into account the identified prospects. Attached to this document is a detailed list of my publications.

Embedded devices powered with environmental energy harvesting, have to sustain computation while experiencing unexpected power failures.To preserve the progress across the power interruptions, Non-Volatile Memories (NVMs) are used to quickly save the state. This dissertation first presents an overview and comparison of different NVM technologies, based on different surveys from the literature. The second contribution we propose is a dedicated backup controller, called Freezer, that implements an on-demand incremental backup scheme. This can make the size of the backup 87.7% smaller then a full-memory backup strategy from the state of the art (SoA). Our third contribution addresses the problem of corruption of the state, due to interruptions during the backup process. Two algorithms are presented, that improve on the Freezer incremental backup process, making it robust to errors, by always guaranteeing the existence of a correct state, that can be restored in case of backup errors. These two algorithms can consume 23% less energy than the usual double-buffering technique used in the SoA. The fourth contribution, addresses the scalability of our proposed approach. Combining Freezer with Bloom filters, we introduce a backup scheme that can cover much larger address spaces, while achieving a backup size which is half the size of the regular Freezer approach.; Les appareils embarqués alimentés par la récupération d'énergie environnementale doivent maintenir le calcul tout en subissant des pannes de courant inattendues. Pour préserver la progression à travers les interruptions de courant, des mémoires non volatiles (NVM) sont utilisées pour enregistrer rapidement l'état. Cette thèse présente d'abord une vue d'ensemble et une comparaison des différentes technologies NVM, basées sur différentes enquêtes de la littérature. La deuxième contribution que nous proposons est un contrôleur de sauvegarde dédié, appelé Freezer, qui implémente un schéma de sauvegarde incrémentale à la demande. Cela peut réduire la taille de la sauvegarde de 87,7% à celle d'une stratégie de sauvegarde à mémoire complète de l'état de l'art. Notre troisième contribution aborde le problème de la corruption de l'état, due aux interruptions pendant le processus de sauvegarde. Deux algorithmes sont présentés, qui améliorent le processus de sauvegarde incrémentale de Freezer, le rendant robuste aux erreurs, en garantissant toujours l'existence d'un état correct, qui peut être restauré en cas d'erreurs de sauvegarde. Ces deux algorithmes peuvent consommer $23\%$ d'énergie en moins que la technique de ``double-buffering'' utilisée dans l'état de l'art. La quatrième contribution porte sur l'évolutivité de notre approche proposée. En combinant Freezer avec des filtres Bloom, nous introduisons un schéma de sauvegarde qui peut couvrir des espaces d'adressage beaucoup plus grands, tout en obtenant une taille de sauvegarde qui est la moitié de la taille de l'approche Freezer habituelle.

Embedded devices powered with environmental energy harvesting, have to sustain computation while experiencing un- expected power failures. To preserve the progress across the power interruptions, Non- Volatile Memories (NVMs) are used to quickly save the state. This dissertation first presents an overview and comparison of different NVM technologies, based on different surveys from the literature. The second contribution we pro- pose is a dedicated backup controller, called Freezer, that implements an on-demand incremental backup scheme. This can make the size of the backup 87.7% smaller then a full- memory backup strategy from the state of the art (SoA). Our third contribution addresses the problem of corruption of the state, due to interruptions during the backup process. Two algorithms are presented, that improve on the Freezer incremental backup process, making it robust to errors, by always guaranteeing the existence of a correct state, that can be restored in case of backup errors. These two algorithms can consume 23% less energy than the usual double-buffering technique used in the SoA. The fourth contribution, ad- dresses the scalability of our proposed approach. Combining Freezer with Bloom filters, we introduce a backup scheme that can cover much larger address spaces, while achieving a backup size which is half the size of the regular Freezer approach.; Les appareils embarqués alimentés par la récupération d'énergie environnementale doivent maintenir le calcul tout en subissant des pannes de courant inattendues. Pour préserver la progression à travers les interruptions de courant, des mémoires non volatiles (NVM) sont utilisées pour enregistrer rapidement l'état. Cette thèse présente d'abord une vue d'ensemble et une comparaison des différentes technologies NVM, basées sur différentes enquêtes de la littérature. La deuxième contribution que nous proposons est un contrôleur de sauvegarde dédié, appelé Freezer, qui implémente un schéma de sauvegarde incrémentielle à la demande. Cela peut réduire la taille de la sauvegarde de 87,7% à celle d'une stratégie de sauvegarde à mémoire complète de l'état de l'art. Notre troisième contribution aborde le problème de la corruption de l'état, due aux interruptions pendant le processus de sauvegarde. Deux algorithmes sont présentés, qui améliorent le processus de sauvegarde incrémentielle de Freezer, le rendant robuste aux erreurs, en garantissant toujours l'existence d'un état correct, qui peut être restauré en cas d'erreurs de sauvegarde. Ces deux algorithmes peuvent consommer 23% d'énergie en moins que la technique de ''double-buffering'' utilisée dans l'état de l'art. La quatrième contribution porte sur l'évolutivité de notre approche proposée. En combinant Freezer avec des filtres Bloom, nous introduisons un schéma de sauvegarde qui peut couvrir des espaces d'adressage beaucoup plus grands, tout en obtenant une taille de sauvegarde qui est la moitié de la taille de l'approche Freezer habituelle.

International audience; Hardware prefetchers are mostly undocumented micro-architectural components of the cache hierarchy, with performance and security implications. Intel CPUs feature four named prefetchers whose behaviors are generally unknown. We build CacheObserver, a generic framework to study prefetchers on Intel CPUs and the first to use the Flush+Flush primitive, unlike previous studies using Flush+Reload. We apply this framework to characterize the L2 Stream prefetcher on the Intel Whiskey and Coffee Lake micro-architectures and uncover the behavior of the L2 Stream prefetcher upon the first few accesses in a page. We also uncover interactions at the L2 level between the Stream and the Adjacent Cache Line prefetchers.

International audience; Microcontroller units (MCUs) are often used in Internet of Things nodes that operate intermittently. Such nodes alternate active and inactive phases under strict energy constraints. Typically, the memory system has a significant impact on overall MCU energy consumption. Memory accesses and memory leakage power often dominate the consumption of active and inactive phases, respectively. Emerging Non-Volatile Memory (NVM) technologies have recently enabled the design of nonvolatile MCUs that can significantly reduce energy consumption during inactive phases. However, replacing all memories with emerging NVMs is not necessarily the best solution, as it often results in dynamic power overhead during active phases. Instead, a hybrid memory architecture that combines volatile and non-volatile technologies is a promising alternative. However, designing hybrid memory MCUs is challenging because the technology that best fits a data segment depends on its access pattern during execution (e.g., program memory experiences mostly reads while the stack alternates reads and writes). For a given intermittent application, our goal is to find the best memory architecture based on a data mapping that takes advantage of the different properties of the available memory technologies. To this end, we present MemCork, a tool for hybrid memory architecture exploration in intermittent computing devices. Based on an instrumented execution on a technology-agnostic FPGA prototype, our tool exhaustively explores the possible data mapping and memory architecture combinations to find the most energy-efficient solution. We evaluate MemCork on two representative intermittent applications and find a customised memory architecture and data mapping that reduces energy consumption by up to 23% compared to a fully NVM solution.

International audience; Airborne observation (see J. Toth’s talk)Mobile cameras from the MoMet device (see Da Fonseca’s talk, IMC2021)2 stabilized cameras + RBpi + RMS software2 unstabilized cameras + continuous recording on MacBasler acA1920-155um + 6mm f/1.4 or 12mm f/1.6 lens ; 20 fps

International audience; This paper introduces a formal workflow for modeling software/hardware systems in order to explore the effects of fault injections and evaluate the robustness to fault injection attacks. We illustrate this workflow on four versions of a PIN authentication code, embedding different software countermeasures. The code is symbolically evaluated on two implementations of the RISC-V CV32E40P core: the original implementation from the OpenHW group and an implementation that integrates protection of the pipeline control signals. On the original, unprotected core, our formal workflow exposes various vulnerabilities, including previously unknown ones, whereas, on the protected core, it confirms the effectiveness of the proposed countermeasures.

International audience; The RISC-V Instruction Set Architecture (ISA) is an open-source, modular and extensible ISA. The ability to add new instructions into a dedicated core opens up perspectives to accelerate VM components or provide dedicated hardware IPs to applications running on top. However, the RISC-V ISA design is clashing on several aspects with other ISAs and therefore software historically built around them. Among them, the lack of condition codes and instruction expansion through simple instruction combination. In this paper we present the challenges of porting Cogit, the Pharo's JIT compiler tightly linked to the x86 ISA, on RISC-V. We present concrete examples of them and the rationale behind their inclusion in the RISC-V ISA. We show how those mismatches are solved through design choices of the compilation process or through tools helping development: a VM simulation framework to keep the development in a high-level environment for the most part, an ISA-agnostic test harness covering main VM functionalities and a machine code debugger to explore and execute generated machine code. We also present a way to prototype custom instructions and execute them in the Pharo environment.

National audience; The technological evolution based on the reduction of the transistor size leads to a greater sensitivity leading to faults. Moreover, in a system-on-chip, a faulty interconnect network can largely impact the operation of an application since it carries a large amount of data. Given these two elements, data protection techniques must be developed to mitigate fault impacts on the application. Some works propose to shuffle the bits inside a flit, transferring the fault impacts on the least significant bits. However, these approaches are applied at a fine-grained level, providing effective fault mitigation, but with significant hardware costs. To address this limitation, this work proposes a region-based bit-shuffling technique which sacrifices efficiency in order to reduce hardware costs.; L'évolution technologique s'appuyant sur la réduction de la taille des transistors conduit à une plus grande sensibilité pouvant conduire à des fautes. De plus, au sein d'un système sur puce, un réseaux d'interconnexion fautif peut largement impacter le fonctionnement d'une application puisqu'il transporte une grande quantité de données. Compte tenu des ces deux éléments, des techniques de protection des données doivent être développées pour atténuer l'impact des fautes sur l'application. Des travaux proposent de mélanger les bits à l'intérieur d'un flit, transférant l'impact des fautes sur les bits les moins significatifs. Cependant, ces approches sont appliquées à un niveau de grain fin, fournissant une atténuation des défauts efficace, mais avec des coûts matériels importants. Pour remédier à cette limitation, ce travail propose une technique de brassage de bit par région, qui sacrifie l'efficacité afin de réduire les coûts matériels.

International audience; Approximate Computing (AxC) aims at optimizing the hardware resources in terms of area and power consumption at the cost of a reasonable degradation in computation accuracy. Several design exploration approaches and metrics have been proposed so far to identify the approximation targets, but only a few of them exploit information derived from assertion-based verification (ABV). To fill in the gap, in this paper, we propose an ABV-based methodology to guide the AxC design exploration of behavioral descriptions. Assertions are automatically mined from the simulation traces of the original design to capture the golden behaviours. Then, we define a metric to predict the impact of approximating model statements on the design accuracy. The metric is computed by a function based on the syntax tree of the mined assertions, their support, and the information derived from the variable dependency graph of the design. It is therefore used, together with functional coverage information, in a sorting procedure for AxC design space exploration to select the target statements for approximation.

International audience; With a turnover of more than 4.2 billion euros in 2020 and a 20% share in the value of the French wine industry's exports, the champagne industry represents a considerable weight in the French economy. In this context of significant economic development, the issue of climate change has been added, calling into question the practices and means of production of the sector. The challenges related to global warming and an ever-increasing demand for yield can be addressed using the Internet of Things (IoT) and Artificial Intelligence (AI) technologies to benefit champagne production and answer these challenges. This article presents a solution to optimise Vranken Pommery products' quality and make environmentally friendly decisions by using intelligent sensors distributed as close as possible to the production and storage facilities to collect data. These sensors use LoRaWAN technology and protocol to communicate. The system integrates components capable of hosting artificial intelligence algorithms and using advanced microcontrollers that allow for intelligent communication network implementation while reducing power consumption and deployment costs.

International audience

National audience

International audience; Soberness-in terms of electrical power-of data centers and high-performance computing systems is becoming an important design issue, as the global energy consumption of information technologies is rising at considerable levels. This issue is all the more complex as these systems are increasingly heterogeneous and variable in their behavior, for example, w.r.t. performance and power consumption, and less predictable, thus demanding runtime management and feedback control. This paper addresses the problem of the control of the power allocated to processors and hence their energy consumption and performance. The use of feedback control allows the energy consumption to be reduced by decreasing the speed without losing performance, by exploiting periods where read/write operations slow the progress. Previous works present limitations regarding both modeling (nonlinear models with numerous parameters) and control performance (mainly instability caused by platform variations). We develop a novel adaptive control that is robust to the variety of execution platforms while maintaining the existing global goals of energy management. We evaluate-on a real system using the Grid'5000 testbed-the robustness of the control to changes in initial parameters and to disturbances, and we compare it with the previous proportionalintegral (PI) control. Our adaptive control approach allows for up to 25% energy savings.

International audience; Cloud and High-Performance Computing (HPC) systems are increasingly facing issues of dynamic variability, in particular w.r.t. performance and power consumption. They are becoming less predictable, and therefore demand more runtime management by feedback loops. In this work, we describe results addressing autonomic administration in HPC systems through a control theoretical approach. We more specifically consider the need for controllers that can adapt to variations a long time in the behavior of controlled systems, but also to being reused on different systems and processors. We therefore explore the application of Model-Free Control (MFC) in the context of resource harvesting in a Computing Grid, by regulating the injection of flexible jobs while limiting perturbation of the prioritary applications.

International audience; With the advent of multi-many-core processors and hardware accelerators, choosing a specific architecture to renew a supercomputer can become very tedious. This decision process should consider the current and future parallel application needs and the design of the target software stack. It should also consider the single-core behavior of the application as it is one of the performance limitations in today's machines. In such a scheme, performance hints on the impact of some hardware and software stack modifications are mandatory to drive this choice. This paper proposes a workflow for performance projection based on execution on an actual processor and the application's behavior. This projection evaluates the performance variation from an existing core of a processor to a hypothetical one to drive the design choice. For this purpose, we characterize the maximum sustainable performance of the target machine and analyze the application using the software stack of the target machine. To validate this approach, we apply it to three applications of the CORAL benchmark suite: LULESH, MiniFE, and Quicksilver, using a single-core of two Arm-based architectures: Marvell ThunderX2 and Arm Neoverse N1. Finally, we follow this validation work with an example of design-space exploration around the SVE vector size, the choice of DDR4 and HBM2, and the software stack choice on A64FX on our applications with a pool of three source architectures: Arm Neoverse N1, Marvell ThunderX2, and Fujitsu A64FX.

International audience