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We report on the use of InGaAsP strain-compensated superlattices (SC-SLs) as a technique to reduce the defect density of Indium Phosphide (InP) grown on silicon (InP-on-Si) by Metal Organic Chemical Vapor Deposition (MOCVD). Initially, a 2 μm thick gallium arsenide (GaAs) layer was grown with very high uniformity on exact oriented (001) 300 mm Si wafers; which had been patterned in 90 nm V-grooved trenches separated by silicon dioxide (SiO₂) stripes and oriented along the [110] direction. Undercut at the Si/SiO₂ interface was used to reduce the propagation of defects into the III-V layers. Following wafer dicing; 2.6 μm of indium phosphide (InP) was grown on such GaAs-on-Si templates. InGaAsP SC-SLs and thermal annealing were used to achieve a high-quality and smooth InP pseudo-substrate with a reduced defect density. Both the GaAs-on-Si and the subsequently grown InP layers were characterized using a variety of techniques including X-ray diffraction (XRD); atomic force microscopy (AFM); transmission electron microscopy (TEM); and electron channeling contrast imaging (ECCI); which indicate high-quality of the epitaxial films. The threading dislocation density and RMS surface roughness of the final InP layer were 5 × 10⁸/cm² and 1.2 nm; respectively and 7.8 × 10⁷/cm² and 10.8 nm for the GaAs-on-Si layer.

Selectively growing epitaxial material in confined dielectric structures has been explored recently as a pathway to integrate highly mismatched materials on silicon substrates. This approach involves the fabrication of a channel-like structure of dielectric material that from the growth atmosphere reaches down to a small exposed area of the substrate where subsequent growth via metal organic chemical vapor deposition (MOCVD) initiates. The technique, referred to as template assisted selective epitaxy, can also enable the development of novel nanoscale photonic and electronic device structures because of its ability to allow epitaxy to progress in a direction, final size, and aspect ratio defined by the dielectric template, and allows integration of horizontal heterojunction inside the channel. To date, most confined epitaxy work has been detailed on silicon. Due to the reduced chemical and thermal stability of InP compared to Si, additional steps for surface preparation are required. In this work, two different fabrication routes are described on InP substrates: one involving amorphous silicon as a sacrificial layer and deposited SiO2 as top oxide, while the other involves spin coated photoresist and hydrogen-silsesquioxane sourced SiOx. Both routes, leading to similar template structures, are demonstrated and discussed. Homoepitaxy of InP in both types of templates and the integration of an InAs horizontal heterojunction are demonstrated via MOCVD. An increase in growth rate with decreasing template length, increasing template width, and decreasing pattern density is observed. [ABSTRACT FROM AUTHOR]