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Computer wargame is a simulation tool that describes war operations. Force maneuver is the foundation of operations, and path planning is the core content. Path planning is simplified as the solution of the shortest path in graph theory. However, the tactical path is not equivalent to the shortest path. Considering the complexity of battlefield maneuvering, information diversity, dynamics and other characteristics, the use of a decisionmaking method that separates battlefield situation and path planning can lead to operational failure. This article provides a tactical path planning method that effectively integrates battlefield situation and map information. This method, based on traditional A* algorithm, combines influence map to digitize battlefield situation factors, and uses digitized situation factors combined with terrain factors as the objective function of the improved A* algorithm. Thus, under the same algorithm complexity conditions, the A* algorithm converges to the tactically optimal path. Simulation experiments effectively verify that this method can support more complex and diverse tactical path planning compared to traditional A* algorithm. Battlefield situation information can guide path planning to effectively reduce the damage suffered by one party during maneuvering and improve our offensive capabilities, shaping a generally advantageous situation. [ABSTRACT FROM AUTHOR]

Instruction stream delivery and instruction Cache failure are two of the important reasons for processor energy dissipation. Programs based on loosely coupled RISC instruction sets exacerbate such energy consumption. Cache-limited network devices such as routers and switches suffer more performance degradation and power consumption due to instruction related processing. This paper focuses on network packet forwarding，which is one of the most important network functions. Thought analyzing instruction characteristics of network packet forwarding, we redefine the RV32 compressed instruction extension set based on the RISC-V instruction set architecture and test it by Spike simulator. Experimental results show that the optimized compression rate is reduced to 70 M and the dynamic instruction compression rate is 90%. Meanwhile, under the same Cache conditions, our RV32C set can reduce the instruction Cache failure by 30 M~70% in comparison to the standard RISC-V set. [ABSTRACT FROM AUTHOR]