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In this work, the potential of 2D semi‐metallic PtSe2 as source/drain (S/D) contacts for 2D material field‐effect‐transistors (FETs) through theoretical and experimental investigations, is explored. From the density functional theory (DFT) calculations, semi‐metallic PtSe2 can inject electrons and holes into MoS2 and WSe2, respectively, indicating the feasibility of PtSe2 contacts for both n‐ and p‐metal‐oxide‐semiconductor FETs (n‐/p‐MOSFETs). Indeed, experimentally fabricated flake‐level MoS2 n‐MOSFETs and WSe2 p‐MOSFETs exhibit a significant reduction in contact resistance with semi‐metallic PtSe2 contacts compared to conventional Ti/Au contacts. To demonstrate the applicability for large‐area electronics, MoS2 n‐MOSFETs are fabricated with semi‐metallic PtSe2 contacts using chemical vapor deposition‐grown MoS2 and PtSe2 films. These devices exhibit outstanding performance metrics, including high on‐state current (≈10−7 A/µm) and large on/off ratio (>107). Furthermore, by employing these high‐performance MoS2 n‐MOSFETs, vertically stacked n‐MOS inverters are successfully demonstrated, suggesting that 3D integration of 2D material FETs is possible using semi‐metallic PtSe2 contacts. [ABSTRACT FROM AUTHOR]

Photonics integrated circuits (PICs) can overcome the bottlenecks in communication capacity. 3D PIC technology is an attractive method for increasing density effectively and combining different materials on one chip for functional integration. In this study, a low‐cost and reconfigurable 3D integrated silicon photonics (SiPhs) platform is proposed fabricated by depositing polycrystalline silicon (poly‐Si) on crystalline silicon (c‐Si), which is patterned through deep ultraviolet (DUV) stepper‐based manufacturing process. The high mobility of poly‐Si ensures high‐speed and power‐efficient modulation. Based on the proposed 3D SiPhs platform, an 8 × 8 optical switch whose units are separated in different layers is fabricated and packaged. The switch shows average insertion losses of −13.98 and −15.86 dB, while working in “all‐cross” and “all‐bar” states, respectively. The crosstalk is lower than −19 and −11 dB for “all‐cross” and “all‐bar” states. Additionally, an overlayer switch located on the 1st and 3rd layers is proposed and experimentally demonstrated, which offers overlapping capabilities that are more compact compared with switches in a single‐layer platform. This validates the possibility of the large‐density integration scalability of the platform. [ABSTRACT FROM AUTHOR]

The emerging nonvolatile memory, three-dimensional vertical resistive random-access memory (VRRAM), inspired by the vertical NAND structure, has been proposed to replace NAND flash memory which has reached its integration limit. To improve the vertical ionic diffusion occurring in the conventional VRRAM structure, we propose a Pt/HfO2/TiO2/Ti self-aligned VRRAM with physically confined switching cells through sidewall thermal oxidation. We achieved stable bipolar switching, endurance (>104 cycles), and retention (>104 s) responses, and improved the interlayer leakage current issue through a distinctive self-aligned structure. Additionally, we elucidated the switching mechanism by analyzing current levels concerning ambient temperature. To utilize VRRAM for neuromorphic computing, the biological synaptic functions are emulated by applying pulse stimulation to the synaptic cell. The weight modulation of biological synapses is demonstrated based on potentiation, depression, spike-rate-dependent plasticity, and spike-timing-dependent plasticity. Additionally, we improve the pattern recognition rate by creating a linear conductance modulation with an incremental pulse train in pattern recognition simulations. The stable electrical characteristics and implementation of various synaptic functions demonstrate that self-aligned VRRAM is suitable for neuromorphic systems as a high-density synaptic device. [ABSTRACT FROM AUTHOR]

Direct printing of conjugated polymer thin‐film transistors enables the fabrication of deformable devices with low cost, high throughput, and large area. However, a relatively poor device performance of printed devices remains a major obstacle to their application in high‐end display backplanes and integrated circuits. In this study, high‐performance and highly stackable printed organic transistors is developed, arrays, and circuits using a near‐amorphous polymer, indacenodithiophene‐co‐benzothiadiazole (IDT‐BT). The printed devices exhibited high saturation mobility (>1 cm2 V−1 s−1), high on/off ratio (>107), and low subthreshold slope (245 mV dec−1). In addition, 16 × 16 printed IDT‐BT arrays achieved 100% fabrication yield, with excellent device‐to‐device uniformity and low variations of mobility (9.55%) and threshold voltage (4.51%), and good operational and environmental stability (>365 days). Furthermore, five stacked 3D transistors are demonstrated with an excellent 3D uniformity without compromising device performance due to a low required thermal budget for processing amorphous IDT‐BT. Finally, a new concept of 3D universal logic gate with high voltage gain (33.91 V/V) and record density (100 printed transistors per cm2) is proposed and fabricated, which is relevant for the commercialization of low‐cost printed display backplanes and high‐density integrated circuits based on highly processable polymeric semiconductors. [ABSTRACT FROM AUTHOR]

In this study, we focus on the development of key processes towards wafer-scale 3-dimentional/vertical (3D) integration of Indium-Phosphide (InP) photonic membranes on InP electronics via adhesive bonding. First, we identified the most critical steps and optimized them to achieve high thermal and mechanical compatibility of components for the co-integration process. Next, we developed a strategy for InP-to-InP wafer bonding with high topology tolerance, and introduced hard benzocyclobutene (BCB) anchors to preserve the alignment and BCB thickness uniformity after bonding. The resulting bond layer is homogeneous in terms of physical and mechanical properties. Finally, we developed a novel method to selectively remove the InP substrate from the photonics side via wet etching while protecting the electronics carrier wafer with hermetic multi-layer coatings. The investigation of these key steps is essential for scalable 3D integration of photonics and electronics at ultra short distances (< $15 ~\mu \text{m}$). [ABSTRACT FROM AUTHOR]

Cu‐Sn transient‐liquid‐phase bonding has a limit in achieving small diameter/high‐density bumps due to the extrusion of the melted Sn layer during bonding. This paper report a new method that can fabricate small diameter Cu‐Sn bumps with 5 μm diameter and 25 μm pitch based on a new thermal reflow and pre‐bonding method that enables solid‐state Cu‐Sn reaction for avoiding Sn extrusion. Using the new method, 3D integration of a 640 × 480 MEMS array on a CMOS circuit chip has been demonstrated. This method can be used in 3D integration of MEMS arrays and CMOS circuits such as micromirror arrays. © 2024 Institute of Electrical Engineer of Japan and Wiley Periodicals LLC. [ABSTRACT FROM AUTHOR]

Three-dimensional (3D) integration has become a leading approach in chip packaging. The interconnection density and reliability of micro-bumps in chip stacking are often threatened by high bonding temperatures. The method of building chip-to-chip interconnections by electroless deposition of metal has its distinct merit, while the interfacial defect issue, especially that related to voiding during the merging of opposite sides, remains largely unsolved. In this study, to trace the influencing factors in the voiding, the growth characteristics of the electroless all-copper interconnections were examined by carrying out deposition experiments in a microfluidic channel device. The results show that when the gap between the opposite copper bumps to be electrolessly merged is as low as 10 μm, significant voids appear at the inflow side and the top of the copper bumps because the hydrogen cannot be expelled in time. A finite-element flow model of the plating solution between the chips was established, which showed that the flow rate of the plating solution around the copper bumps was much higher than in the merging gap, causing an uneven supply of reactants. Based on these findings, we proposed two potential solutions, one is to improve the flow mode of the plating solution, and the other is to add the reaction inhibitor, 2,2′-bipyridine. Finally, the combination of these two approaches successfully achieved an improved merging quality of the copper joints. [ABSTRACT FROM AUTHOR]

This article presents a novel bonding method for chip packaging applications in the semiconductor industry, with a focus on downsizing high-density and 3D-stacked interconnections to improve efficiency and performance. Microfluidic electroless interconnections have been identified as a potential solution for bonding pillar joints at low temperatures and pressures. However, the complex and time-consuming nature of their production process hinders their suitability for mass production. To overcome these challenges, we propose a tailored plating solution using an enhanced copper concentration and plating rate. By eliminating the need for fluid motion and reducing the process time, this method can be used for mass production. The Taguchi approach is first used to optimize the copper–quadrol complex solution with the plating rate and decomposition time. This solution exhibits a copper concentration that is over five times higher than that of conventional solutions, a plating rate of 22.2 μm/h, and a decomposition time of 8 min on a Cu layer substrate. This technique enables Cu pillars to be successfully bonded within 7 min at 35 °C. Planarizing the pillar surface yields a high bonding percentage of 99%. Mechanical shear testing shows a significant fracture strength of 76 MPa. [ABSTRACT FROM AUTHOR]

Heterogeneous integration helps to maximize the performance of photonics or electronics devices by leveraging the strengths of diverse material platforms within a unified process flow. A promising approach is the 3D integration of InP photonic or electronic membranes to other substrate materials containing photonics or electronics ICs via adhesive bonding. However, wafer-scale spatial distortions arising from the bonding process can compromise fabrication. Herein, we used electron-beam metrology to investigate the distortion of InP membranes resulting from wafer-scale bonding with benzocyclobutene (BCB). We measured both the linear and residual components of distortions across the tested wafers. First, bonding of InP substrate with BCB on various carrier substrates (Si, InP, SiC, and glass) was realized, which unveiled post-bonding membrane expansion factors in the range of ~0-325 ppm and beyond that for the glass carrier. The diversion of these values from theoretical estimations was linked to the adhesive bonding process. Next, we examined the effect of BCB thickness in the ranges of 1- $12\mu $ m, residual mechanical stress, and the impact of defects on distortions. Using these findings, we experimentally verified that the largest part of distortions can be efficiently pre-compensated to overcome the challenges of multilayer overlay errors in the fabrication of heterogeneously integrated photonic and electronic devices.

In this work, we studied the characteristics of Cu-Cu bonding with a ruthenium passivation layer at low temperatures. It is confirmed that the ruthenium passivation layer is effective in preventing the formation of native copper oxide, and diffusion of the copper into the ruthenium passivation layer occurred sufficiently at 200°C. The Cu samples with the ruthenium passivation layer were successfully bonded at 200°C. They exhibited excellent shear strength of 17.16 MPa, and the specific contact resistance of $1.78\times 10 ^{-7}~\Omega \cdot $ cm2 at the bonding interface. With the results, we expect that along with improving the thermal budget of the bonding process, it will be able to contribute to improving the chip performance and reliability of heterogeneous integrated structures.

The relentless pace of transistor miniaturization has enabled developers to continuously increase chip complexity since the beginning of the information age. However, as transistors get smaller and chips become larger, the cost of manufacturing ICs becomes increasingly prohibitive. As Moore’s Law is coming to an end, industry and academia have been exploring new paradigms to keep up with the ever-increasing demand for performance and functionality while dealing with the constraints of power consumption, area, and yield. In this context, 3DICs are considered the future of the IC industry as they enable designers to fulfill both the “More Moore” and the “More than Moore” paradigm. A key feature of the 3DIC is that it can be manufactured by assembling multiple chiplets. Chiplets are single-purpose dies that must be assembled with other chiplets to form a complete system. Researchers and industry leaders believe that a chiplet market will form and that products with off-the-shelf chiplets will emerge. This scenario offers many economic opportunities. However, it also raises concerns regarding the security and trust (S&T) of chiplet-based designs. Malicious chiplets, hardware trojans, and chiplet intellectual property theft are threats that must be addressed as the industry moves towards the “chiplet age”. In this survey, we introduce the different types of 3DICs and their production chain. We then define the threats that threaten the different steps of the 3DIC manufacturing process. Finally, we present and discuss the state of the art in hardware S&T techniques for chiplet-based 3DICs.

Introduction. Through-silicon-via (TSV) is one of the most important components of 3D integrated circuits. Similar to two-dimensional circuits, the performance evaluation of 3D circuits depends on both the quality factor and inductance. Therefore, accurate TSV-inductor modeling is required for the design and analysis of 3D integrated circuits. Aim. This work proposes the equivalent circuit model of the TSV-inductor to derive the relations that determine both the quality factor and the inductance by Y-parameters. Methods. The model developed was simulated using MATLAB software, and it was used to evaluate the effect of redistribution lines width, TSV radius, and the number of turns on inductance and quality factor. Additionally, a comparative study was presented between TSV-based inductors and conventional inductors (i.e., spiral and racetrack inductors). Results. These studies show that replacing conventional inductors with TSV-inductors improved the quality factor by 64 % compared to a spiral inductor and 60 % compared to a racetrack inductor. Furthermore, the area of the TSV-inductor was reduced up to 1.2 mm². Using a PSIM simulator, the application of an integrated TSV-inductor in a buck converter was studied, and the simulation gave very good results in 3D integration compared to 2D integration. Moreover, the simulation results demonstrated that using a TSV-inductor in a buck converter could increase its efficiency by up to 15 % and 6 % compared to spiral and racetrack inductors, respectively.

Introduction. Through-silicon-via (TSV) is one of the most important components of 3D integrated circuits. Similar to two-dimensional circuits, the performance evaluation of 3D circuits depends on both the quality factor and inductance. Therefore, accurate TSV-inductor modeling is required for the design and analysis of 3D integrated circuits. Aim. This work proposes the equivalent circuit model of the TSVinductor to derive the relations that determine both the quality factor and the inductance by Y-parameters. Methods. The model developed was simulated using MATLAB software, and it was used to evaluate the effect of redistribution lines width, TSV radius, and the number of turns on inductance and quality factor. Additionally, a comparative study was presented between TSV-based inductors and conventional inductors (i.e., spiral and racetrack inductors). Results. These studies show that replacing conventional inductors with TSV-inductors improved the quality factor by 64 % compared to a spiral inductor and 60 % compared to a racetrack inductor. Furthermore, the area of the TSV-inductor was reduced up to 1.2 mm². Using a PSIM simulator, the application of an integrated TSV-inductor in a buck converter was studied, and the simulation gave very good results in 3D integration compared to 2D integration. Moreover, the simulation results demonstrated that using a TSV-inductor in a buck converter could increase its efficiency by up to 15 % and 6 % compared to spiral and racetrack inductors, respectively. [ABSTRACT FROM AUTHOR]

The human brain possesses an exceptional information processing capability owing to the 3D and dense network architecture of numerous neurons and synapses. Brain‐inspired neuromorphic hardware can also benefit from 3D architectures, such as high integration of circuits and acquisition of highly complex dynamical systems. In this study, for future 3D neuromorphic engineering, 3D conductive polymer networks consisting of poly(3,4‐ethylenedioxy‐thiophene) doped with poly(styrene sulfonate) anions (PEDOT:PSS) are successfully and stably fabricated between multiple electrodes from scratch in precursor solution by electropolymerization. The networks efficiently emulate the 3D local connections between neighboring neurons observed in the cortex. This novel technology, which allows 3D conductive wiring only between desired electrodes, is unprecedented and has potential as an underlying technology for 3D integration. Furthermore, the experimental results also conclusively prove that conductance modification can be performed by manipulating the physical and chemical properties of 3D branch‐wired conductive polymer wires, thus demonstrating for the first time the feasibility of neuromorphic wetware with enhanced biological plausibility in the subsequent post‐Moore era. [ABSTRACT FROM AUTHOR]

Three-dimensional (3D) integration has become a leading approach in chip packaging. The interconnection density and reliability of micro-bumps in chip stacking are often threatened by high bonding temperatures. The method of building chip-to-chip interconnections by electroless deposition of metal has its distinct merit, while the interfacial defect issue, especially that related to voiding during the merging of opposite sides, remains largely unsolved. In this study, to trace the influencing factors in the voiding, the growth characteristics of the electroless all-copper interconnections were examined by carrying out deposition experiments in a microfluidic channel device. The results show that when the gap between the opposite copper bumps to be electrolessly merged is as low as 10 μm, significant voids appear at the inflow side and the top of the copper bumps because the hydrogen cannot be expelled in time. A finite-element flow model of the plating solution between the chips was established, which showed that the flow rate of the plating solution around the copper bumps was much higher than in the merging gap, causing an uneven supply of reactants. Based on these findings, we proposed two potential solutions, one is to improve the flow mode of the plating solution, and the other is to add the reaction inhibitor, 2,2′-bipyridine. Finally, the combination of these two approaches successfully achieved an improved merging quality of the copper joints.

It is becoming quite evident that, when it comes to the further scaling of advanced node transistors, increasing the flash memory storage capacity, and enabling the on-chip integration of multiple functionalities, "there's plenty of room at the top". The fabrication of vertical, three-dimensional features as enablers of these advanced technologies in semiconductor devices is commonly achieved using plasma etching. Of the available plasma chemistries, SF6/O2 is one of the most frequently applied. Therefore, having a predictive model for this process is indispensable in the design cycle of semiconductor devices. In this work, we implement a physical SF6/O2 plasma etching model which is based on Langmuir adsorption and is calibrated and validated to published equipment parameters. The model is implemented in a broadly applicable in-house process simulator ViennaPS, which includes Monte Carlo ray tracing and a level set-based surface description. We then use the model to study the impact of the mask geometry on the feature profile, when etching through circular and rectangular mask openings. The resulting dimensions of a cylindrical hole or trench can vary greatly due to variations in mask properties, such as its etch rate, taper angle, faceting, and thickness. The peak depth for both the etched cylindrical hole and trench occurs when the mask is tapered at about 0.5°, and this peak shifts towards higher angles in the case of high passivation effects during the etch. The minimum bowing occurs at the peak depth, and it increases with an increasing taper angle. For thin-mask faceting, it is observed that the maximum depth increases with an increasing taper angle, without a significant variation between thin masks. Bowing is observed to be at a maximum when the mask taper angle is between 15° and 20°. Finally, the mask etch rate variation, describing the etching of different mask materials, shows that, when a significant portion of the mask is etched away, there is a notable increase in vertical etching and a decrease in bowing. Ultimately, the implemented model and framework are useful for providing a guideline for mask design rules. [ABSTRACT FROM AUTHOR]

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This paper discusses the multi-domain modeling and simulation issues of the design and analysis of heterogeneous integrated systems. Modeling and simulation method- ology and tools are also discussed.

This paper deals with the converter design dedicated to an electromagnetic actuator array (EAA). An adaptive converter network based on full-bridge is proposed. Actuators in the same column or row are connected in series and are driven by the same full-bridge. In order to control each actuator independently, four-quadrant switches are inserted in series and in parallel to activate or deactivate the corresponding actuator. Integration constraints with this EAA imply a 3D design. The global control is investigated to realize the coordinated control of EAA. Dynamic interleaved phase strategy is proposed to minimize the input current ripple. A prototype of converter network dedicated to a 2 × 2 EAA has been fabricated. This prototype validates the compact 3D-integration of converter network and EAA. Experimental results with the fabricated prototype show that the dynamic interleaved phase reduces the current ripple as expected and validate the coordinated control of EAA. More generally, this paper presents a scalable converter design for the EAA and studies the global control of the converter network.

Synchrotron x-ray microdiffraction has been applied to TSV characterization in various studies for nondestructive inspection with submicron resolution due to its high beam intensity and penetration depth. In this paper, the application of this technique to TSV investigations is examined and the correlation of the plastic deformation to the microstructure and extrusion behavior along with the effect of TSV dimensional scaling is examined. It is shown that the variability of the copper microstructure and resulting TSV behavior requires a larger number of samples in order to report statistically significant observations. The role of the microstructure in creating statistical scatter is demonstrated through microdiffraction measurements of grain orientation correlated with the observed peak widening, which shows that degraded TSV reliability is largely due to the high elastic anisotropy of copper. After taking the statistical variations into account, the scaling effect was clearly observed, with larger plastic deformation in 2μm diameter TSVs than in 5μm diameter TSVs consistent with microstructure variations. This is confirmed by TSV extrusion measurements, which show that the magnitude and statistical spread of the via extrusion for the 2μm diameter TSVs is higher than that of the 5μm diameter TSVs. These results, validated by thermomechanical simulation, demonstrate first that large sample sizes are required in copper TSV investigations due to high variability, which is not improved with scaling.

In this paper, first, a broad overview of existing covert channel communication-based security attacks is provided. Such covert channels establish a communication link between two entities that are not authorized to share data. The secret data is encoded into different forms of signals, such as delay, temperature, or hard drive location. These signals and information are then decoded by the receiver to retrieve the secret data, thereby mitigating some of the existing security measures. The important steps of covert channel attacks are described, such as data encoding, communication protocol, data decoding, and models to estimate communication bandwidth and bit error rate. Countermeasures against covert channels and existing covert channel detection techniques are also summarized. In the second part of the paper, the implications of such attacks for emerging packaging technologies, such as 2.5D/3D integration are discussed. Several covert channel threat models for 2.5D/3D ICs are also proposed. [ABSTRACT FROM AUTHOR]

Three-dimensional integrated packaging with through-silicon vias (TSV) can meet the requirements of high-speed computation, high-density storage, low power consumption, and compactness. However, higher power density increases heat dissipation problems, such as severe internal heat storage and prominent local hot spots. Among bulk materials, diamond has the highest thermal conductivity (≥2000 W/mK), thereby prompting its application in high-power semiconductor devices for heat dissipation. In this paper, we report an innovative bottom-up Cu electroplating technique with a high-aspect-ratio (10:1) through-diamond vias (TDV). The TDV structure was fabricated by laser processing. The electrolyte wettability of the diamond and metallization surface was improved by Ar/O plasma treatment. Finally, a Cu-filled high-aspect-ratio TDV was realized based on the bottom-up Cu electroplating process at a current density of 0.3 ASD. The average single-via resistance was ≤50 mΩ, which demonstrates the promising application of the fabricated TDV in the thermal management of advanced packaging systems. [ABSTRACT FROM AUTHOR]

Epoxy molded compounds (EMCs) containing a high percentage of filler in the form of silicon oxide particles are used to reduce the difference in the temperature coefficient of linear expansion between the die and the sealing material when dies packaging in plastic. However, in addition to the die, the commutation substrate has a significant effect on the level of thermomechanical stresses in the package. In the 3D integration in a microassembly, vertical interconnects combines several substrates that can be made from different dielectrics. This paper shows that sealing materials with different temperature coefficients of linear expansion in the outer and inner parts of the product can reduce the level of thermal stresses in such a structure. The dependences of the thermomechanical stress and deformation of the microassembly on the number of levels and the amount of filler in the outer sealing compound are determined. The study is carried out by the computer simulation of various designs of microassemblies sealed with compounds with different values of the temperature and mechanical parameters. Based on the obtained dependency graphs, the optimal values of the filler content in the outer and inner compounds are established to ensure the minimum temperature and mechanical (under the action of acceleration) deformation of microassemblies at a different number of levels. [ABSTRACT FROM AUTHOR]

Low-power-consumption optical devices are crucial for large-scale photonic integrated circuits (PICs). In this paper, a three-dimensional (3D) polymer variable optical attenuator (VOA) is proposed. For monolithic integration of silica and polymer-based planar lightwave circuits (PLCs), the vertical VOA is inserted between silica-based waveguides. Optical and thermal analyses are performed through the beam propagation method (BPM) and finite-element method (FEM), respectively. A compact size of 3092 μm × 4 μm × 7 μm is achieved with a vertical multimode interference (MMI) structure. The proposed VOA shows an insertion loss (IL) of 0.58 dB and an extinction ratio (ER) of 21.18 dB. Replacing the graphene heater with an aluminum (Al) electrode, the power consumption is decreased from 29.90 mW to 21.25 mW. The rise and fall time are improved to 353.85 μs and 192.87 μs, respectively. The compact and high-performance VOA shows great potential for a variety of applications, including optical communications, integrated optics, and optical interconnections. [ABSTRACT FROM AUTHOR]

Abstract In this article, antennas for the 60 GHz ISM band designed to be integrated to a new high-frequency, low-cost interposer technology called Membrane-nanowire-Membrane (MnM) are discussed, manufactured, and measured. Also, an antenna characterization system under development at the Microelectronic Laboratory (LME-USP) is introduced, showing promising results for the deployment of mmW systems.

Three-dimensional (3D) integration is considered an effective approach to extend and expand Moore's Law. Among them, Through-Silicon Via (TSV) technology provides mechanical support, heat conduction, and electrical connections for vertically stacked chips. The multilayer interface structure of TSV and the significant differences in the coefficient of thermal expansion (CTE) between layers can lead to complex thermal stress in TSV structures under heating conditions, which can degrade the performance of Three-Dimensional Integrated Circuits (3D ICs). This article systematically summarizes the current research status of copper pillar extrusion protrusions, Cu/Si interface integrity damage, and carrier mobility changes caused by thermal stress, focusing on the failure mechanisms and models of each aspect, elucidating the influencing factors and potential destructive failures. It then outlines and compares the advantages and disadvantages of micro-Raman spectroscopy, bending beam technology, and synchrotron X-ray microdiffraction technology in characterizing thermal stress in TSV structures. Characterizing thermal stress is beneficial for determining stress distribution and reliability risks of TSV. Finally, based on the analysis of the reliability impacts of the three major aspects mentioned above, measures to reduce the reliability impacts of thermal stress from the perspectives of heat dissipation, structure, materials, and processes in recent years are summarized. This article aims to deepen researchers' understanding of the main failure modes caused by thermal stress on TSV structures and provide theoretical guidance for building stable and reliable TSV structures. [ABSTRACT FROM AUTHOR]

Achieving high performance, multifunctionality, and a compact size simultaneously in a single T/R module presents a significant challenge. In this work, both the 'chiplet' technique and 3D integration technique are adopted to form a T/R microsystem using self-matching interconnectors. Such T/R microsystem consists of four GaAs chips and one CMOS chip. The designed microsystem with a small size is utilized for the application of tile-type mmWave active phased array. Its measured results demonstrate good performance in terms of high gain, large output power, 6-bit phase shift, and 6-bit attenuation, confirming the effectiveness of our adopted architecture and design method. As such, this work provides a valuable design guideline for the chiplet-based 3D integrated RF microsystem. [ABSTRACT FROM AUTHOR]

Continued scaling in accordance with Moore’s law is becoming increasingly difficult. Pitch shrinkage and standard cell height reduction via design technology co-optimization with design rules have sustained this scaling until recently. However, we observe that standard cell device scaling is becoming saturated due to yield and cost. One way to continue device footprint reduction is by expanding in the third dimension via monolithic 3D integration, using for example stacked gate-all-around (GAA) devices, complementary FETs, vertical FETs, and 3D logic. However, using these footprint scaling approaches to increase device density creates new problems. Using vertical gate-all-around FET (VFET) technologies as a specific instance of 3D device scaling, we demonstrate that the key bottleneck to footprint scaling is the pin density wall. The footprint of a block is predominantly limited by the pin density as we increase the number of active device layers. While a full-blown paradigm shift on layout methodology, design flow, and electronic design automation (EDA) platform is not available now, we describe in this article three specific baby steps that can alleviate the pin density problem and demonstrate their potential benefits for footprint scaling: (1) allocating standard cell pin sideways and using block-level routing with the local interconnect layers; (2) using the backside of the substrate for the power distribution network; and (3) using the generation of more complex standard cells. We show via several core designs that a 42.6% reduction in the core area is achievable when a combination of these operations is employed.

To achieve complex functionality with small size, weight and power, photonic integrated circuits (PIC) are expanded from two-dimensional (2D) to three-dimensional (3D). In this paper, a new design for a scalable 3D silicon optical switch is proposed. Key elements, including silicon electro-optic switches, crossings, and interlayer transitions are used to define and optimize the 3D optical switching network. The architecture is based on CLOS architecture, which can be extended to multiple layers. Silicon-based two- and three-layer switches are carefully designed and analyzed as an example based on the transfer matrix technique (TMT). In a 4×4 two-layer optical switch, the average insertion loss at 1550 nm wavelength is ∼4.16 dB, and ∼3.69 dB for the “all-cross” and “all-bar” states, respectively. In a 4×4 three-layer optical switch, the average insertion loss at 1550 nm wavelength is ∼5.96 dB, and ∼5.41 dB for the “all-cross” and “all-bar” states, respectively. The architecture also shows the scalability of both the port number and the layer number. The scalable 3D architecture proposed could improve the interconnect density twice and thrice in a single-layer design.

Cu-to-Cu direct bonding plays an important role in three-dimensional integrated circuits (3D IC). However, the bonding process always requires high temperature, high pressure, and a high degree of consistency in height. In this study, Sn is passivated over electroplated copper. Because Sn is a soft material and has a low melting point, a successful bond can be achieved under low temperature and low pressure (1 MPa) without any planarization process. In this experiment, Sn thickness, bonding temperature, and bonding pressure are variables. Three values of thicknesses of Sn, i.e., 1 μm, 800 nm, and 600 nm were used to calculate the minimum value of Sn thickness required to compensate for the height difference. Additionally, the bonding process was conducted at two temperatures, 220 °C and 250 °C, and their optimized parameters with required pressure were found. Moreover, the optimized parameters after the Cu planarization were also investigated, and it was observed that the bonding can succeed under severe conditions as well. Finally, transmission electron microscopy (TEM) was used to observe the adhesion property between different metals and intermetallic compounds (IMCs). [ABSTRACT FROM AUTHOR]

The new generation of data centers is further evolving towards the direction of high speed and intelligence, which puts forward a great demand for the iteration of optical interconnection technology. Three-dimensional integration based on active photonic interposers can achieve the advantages of high integration, high bandwidth and low power consumption, which has become the main direction for next generation optical module technology. The fabrication and assembly of 3D optical modules based on active interposer-integrated edge couplers and TSV are realized in this paper. Different active interposer processes with integrated edge couplers and RDL-TSV-RDL structures are discussed, manufactured, analyzed and evaluated. The problem of the co-fabrication of the TSV and edge coupler was solved, and perfect electrical and optical characteristics were also achieved. Finally, the fabrication of the substrate and the assembly of the 3D optical module were completed. This paper lays a solid foundation for the further research and large-scale application of 3D optical modules in the future. [ABSTRACT FROM AUTHOR]

The relatively large total device dimension (${L}_{\rm Tot}$) of Ferroelectric-Semiconductor Tunnel Junctions (MFIS-FTJs) strictly obstructs their potential for hyper-scaling 3D integration. Towards such an issue, we propose an engineered MFIS-FTJ with the ultrathin semiconductor electrode (SE). The design rule for MFIS-FTJs with ultrathin SE is also investigated, considering voltage redistribution, SE thickness limitation, and quantum confinement effect. With careful design, our MFIS-FTJs with an 8.5 nm-thick SE achieve an ultrascaled ${L}_{\rm Tot}$ around 10 nm and acquire ~40 times enhancement in the tunneling electroresistance ratio over the bulk reference devices. This opens up a feasible pathway for ${L}_{\rm Tot}$ scaling in MFIS-FTJ and is instructive for practical application. [ABSTRACT FROM AUTHOR]

The state-of-the-art CMOS technology has started to adopt three-dimensional (3D) integration approaches, enabling continuous chip density increment and performance improvement, while alleviating difficulties encountered in traditional planar scaling. This new device architecture, in addition to the efforts required for extracting the best material properties, imposes a challenge of reducing the thermal budget of processes to be applied everywhere in CMOS devices, so that conventional processes must be replaced without any compromise to device performance. Ultra-violet laser annealing (UV-LA) is then of prime importance to address such a requirement. First, the strongly limited absorption of UV light into materials allows surface-localized heat source generation. Second, the process timescale typically ranging from nanoseconds (ns) to microseconds (μs) efficiently restricts the heat diffusion in the vertical direction. In a given 3D stack, these specific features allow the actual process temperature to be elevated in the top-tier layer without introducing any drawback in the bottom-tier one. In addition, short-timescale UV-LA may have some advantages in materials engineering, enabling the nonequilibrium control of certain phenomenon such as crystallization, dopant activation, and diffusion. This paper reviews recent progress reported about the application of short-timescale UV-LA to different stages of CMOS integration, highlighting its potential of being a key enabler for next generation 3D-integrated CMOS devices. [ABSTRACT FROM AUTHOR]

It is becoming quite evident that, when it comes to the further scaling of advanced node transistors, increasing the flash memory storage capacity, and enabling the on-chip integration of multiple functionalities, “there’s plenty of room at the top”. The fabrication of vertical, three-dimensional features as enablers of these advanced technologies in semiconductor devices is commonly achieved using plasma etching. Of the available plasma chemistries, SF6/O2 is one of the most frequently applied. Therefore, having a predictive model for this process is indispensable in the design cycle of semiconductor devices. In this work, we implement a physical SF6/O2 plasma etching model which is based on Langmuir adsorption and is calibrated and validated to published equipment parameters. The model is implemented in a broadly applicable in-house process simulator ViennaPS, which includes Monte Carlo ray tracing and a level set-based surface description. We then use the model to study the impact of the mask geometry on the feature profile, when etching through circular and rectangular mask openings. The resulting dimensions of a cylindrical hole or trench can vary greatly due to variations in mask properties, such as its etch rate, taper angle, faceting, and thickness. The peak depth for both the etched cylindrical hole and trench occurs when the mask is tapered at about 0.5°, and this peak shifts towards higher angles in the case of high passivation effects during the etch. The minimum bowing occurs at the peak depth, and it increases with an increasing taper angle. For thin-mask faceting, it is observed that the maximum depth increases with an increasing taper angle, without a significant variation between thin masks. Bowing is observed to be at a maximum when the mask taper angle is between 15° and 20°. Finally, the mask etch rate variation, describing the etching of different mask materials, shows that, when a significant portion of the mask is etched away, there is a notable increase in vertical etching and a decrease in bowing. Ultimately, the implemented model and framework are useful for providing a guideline for mask design rules.

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Polymer adhesives have emerged as a promising dielectric passivation layer in hybrid bonding for 3D integration, but they raise misalignment problems during curing. In this work, the synergistic effect of oxygen plasma surface activation and wetting is utilized to achieve bonding between completed cured polyimides. The optimized process achieves a void-less bonding with a maximum shear strength of 35.3 MPa at a low temperature of 250 °C in merely 2 min, significantly shortening the bonding period and decreasing thermal stress. It is found that the plasma activation generates hydrophilic groups on the polyimide surface, and the wetting process further introduces more −OH groups and water molecules on the activated polyimide surface. The synergistic process of plasma activation and wetting facilitates the bridging of polyimide interfaces to achieve bonding, providing an alternative path for adhesive bonding in 3D integration. [ABSTRACT FROM AUTHOR]

Fine pitch Cu/SiO2 hybrid bonding has been successfully demonstrated at a low temperature of 120 °C, a breakthrough, using Au passivation method in this work. To explore the bonding mechanism of passivation structures for hybrid bonding in details, Cu-Cu direct bonding with Au passivation on both wafer-level and chip-level has been discussed, including analyses of AFM, SAT, TEM, electrical measurements, and reliability test. Cu/SiO2 hybrid bonding with the fine pitch structure with stable electrical performance can be achieved at low bonding temperature under an atmospheric environment. Accordingly, this Au passivation scheme for Cu/SiO2 hybrid bonding with excellent bonding quality, low thermal budget, and high reliability shows a great feasibility for the 3D IC and heterogenous integration applications.

As a key approach to augment Moore's Law scaling, 3D integration technologies have enabled small form factor, low cost, diverse, modular and flexible assembly of integrated circuits in the semiconductor industry. It is therefore essential to adopt these technologies to the quantum computing devices which are at the nascent stage and generally require large scale integration to be practical. In this review, we focus on four popular quantum bit (qubit) candidates (trapped ion, superconducting circuit, silicon spin and photon) which are encoded by distinct physical systems but all intrinsically compatible with advanced CMOS fabrication process. We introduce the specific scalability bottlenecks of each qubit type and present the current solutions using 3D integration technologies. We evaluate and classify these technologies into three main categories based on the hierarchy. A brief discussion regarding the thermal management is also provided. We believe this review serves to provide some useful insights on the contributions of interconnect, integration and packaging to the field of quantum computing where rapid development is ongoing.

To meet the demand of large number and high integration of filters in the IF filter modules of radar receivers, a miniaturization LC filter based on the 3D integration technology is proposed in this study. The application and integrating process of 3D LC filter in modules are studied and analyzed. The 3D LC filter adopts two substrates, and uses 3D integration process and BGA technology to realize the three-dimensional integrated assembly of the two substrates. High-density layout can be realized by placing capacitive elements on the bottom substrate. Inductive elements are placed on the top substrate and separated from the capacitive elements, and signal communication is achieved through solder balls. The use of a three-dimensional integration scheme can reduce the size of the LC filter circuit by nearly 50%, and the filter index is consistent with the performance of the planar filter circuit. Compared with the traditional IF filter component design method, this solution is more conducive to achieve high integration and miniaturization. [ABSTRACT FROM AUTHOR]

In this paper, first, a broad overview of existing covert channel communication-based security attacks is provided. Such covert channels establish a communication link between two entities that are not authorized to share data. The secret data is encoded into different forms of signals, such as delay, temperature, or hard drive location. These signals and information are then decoded by the receiver to retrieve the secret data, thereby mitigating some of the existing security measures. The important steps of covert channel attacks are described, such as data encoding, communication protocol, data decoding, and models to estimate communication bandwidth and bit error rate. Countermeasures against covert channels and existing covert channel detection techniques are also summarized. In the second part of the paper, the implications of such attacks for emerging packaging technologies, such as 2.5D/3D integration are discussed. Several covert channel threat models for 2.5D/3D ICs are also proposed.