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A structural-topological model of relay and switching circuits is proposed. An algorithm for the simulation of actuation of a relay and switching circuit is described, which is based on the analysis of its topology and the rules governing the action of the relay on the contacts. A special graph algebra is introduced to facilitate the topological analysis of relay and switching circuits. The automatic construction of the diagram of state transitions for a relay and switching circuit by executing input signal scenarios is considered. The execution of scenarios is illustrated using the automatic elimination of asynchronous mode of power system operation.

When users analyze symbolically physical phenomena, software products which partially help them write a symbolic equation to the phenomena are available. In electric engineering, there are a few software products which compute symbolically voltages and currents of electric circuits. They cover the frequency response analysis on behavior of linear time-invariant (LTI) circuits. However, they do not cover symbolic computation on the time response of circuits. This paper introduces a software product which generates a model for computing the time response of LTI circuits.

The paper presents the method of digital modelling of process of switching on by vacuum switch in capacitive circuits. Currently, there are few descriptions of vacuum switch models used for capacitive circuits switching on. More often researchers focus on vacuum switch models used for switching of the circuits (also previous works of the Authors) and even more often models used for switching of the inductive circuits. In this work authors have focused on phenomena of switching on by vacuum switch in capacitive circuits which in the literature is not often described and which in its character differs significantly from the processes taking place during switching off. In the model, presented in this paper, authors proposed beside the voltage-current control a new approach of modelling of the mechanism of contact bounce, based on the Matlab library element “sldemo_bounce”. The verification of the correctness of the model has been done in capacitive circuit during switching on of the capacitor batteries with different parameters (capacities) and neutral point connection. This model have not been analysed in inductive circuits.

Joint entropy is used to quantify the complex nonlinear states of dc-dc switching converters in this brief. The switching instant symbolic sequence (SISS) and the topological structural symbolic sequence (TSSS) are presented based on the characteristics of dc-dc converters. Transforming SISS and TSSS into the decimal symbolic sequences, joint entropy is obtained as the index to quantify the nonlinearity of the dc-dc converter. Finally, a Cuk converter is studied as an example to explain how the joint entropy can quantify the complex state of the dc-dc switching converter.

Based on the characteristics of dc-dc switching converters and the logical arithmetic method of computer that changes to decimal system from binary system, the main switching block is presented to distinguish the switching behaviors and the degree of the converter's complexity during one switching period. The main symbolic sequence is established to clearly show how the switching modes change in one switching period. Adopting the coarse-grained symbolic sequence method, the secondary switching block and secondary symbolic sequence are established in terms of main switching block too. Hence, the duplicate symbolic sequence is put forward to detect bifurcation types in dc-dc switching converters. Based on the duplicate symbolic sequence, the concept of weight complexity is first defined and utilized to analyze border collision and bifurcation phenomena qualitatively along with Lempel-Ziv (L-Z) complexity. The presented weight complexity and the L-Z complexity are combined to introduce the stability index for guiding circuit design of power electronics. Finally, voltage-mode-controlled flyback converter is used as an example to illustrate the applications of the proposed duplicate symbolic sequence and complexity to detect bifurcation behaviors of the switching system.

In this paper, we investigate the problem of designing a switched compensator for a plant switching amongst a finite family of constrained linear time invariant configurations. We assume that switching is governed by a pre-defined switching rule which prescribes that any information pertaining to the time or state dependency of the switching event is unavailable to the controller side. The novelty of the proposed approach relies on its capability to jointly use Command Governor features and one-step ahead controllable set sequences in order to online manage admissible switching occurrences. To this end, the model transition dwell time concept is exploited in order to formally define the conditions under which switching command governor architectures can be safely activated.

This chapter contains documentation of the developed MATLAB software used for development of the models as a part of the learning process. The developed blocks are gathered in three libraries: Relay Elements, Input Signals, and Tools, which will be presented in the following subsections.

Principles of the controlled (synchronous) switching (near zero of the load current) by reed relays of electric AC circuits, electric circuits that embody these principles, as well as the mathematical expressions that determine the parameters of these circuits are considered. Experimental results that have shown good agreement with the theoretical study are shown.

In this paper a novel method for circuit analysis is proposed. It is based on using symbolic analysis in matrix form, which is especially appropriate for repetitive similar calculations of the same circuit. This method, which applies hyper-complex numbers (hypernions), was first developed by the authors for analyzing the non-sinusoidal operation of electrical circuits. Now, the method has been extended to the analysis of electronic/switching circuits in which the sources and/or the parameters are step-wisely changed as a result of switching. Such circuits are common in different kinds of DC-DC converters (such as Buck, Boost, Cuk, etc.). The proposed method gives a new approach to the analysis of the above circuits by opening the possibility of treating them in a general-analytical form, just like in regular electrical circuits having a constant configuration and constant parameters. The computation of such kinds of circuits by using the proposed method becomes very simple, since the circuit does not have to be analyzed many times, each time for a different configuration, but all at once by performing a parallel computation. The theoretical presentation is accompanied by numerical examples.

A method of linearization with respect to the useful signal of relay systems with the control plant containing blocks with limiters is proposed. Relay systems with two-position relay element are considered. The method allows studying the tracking mode of input signals in the relay system in a simple way. This is very important for synthesizing relay systems when a great number of variants need to be analyzed.

We consider relay switching circuits constructed from switches whose operation is described by Boolean functions with external parameters z 1,?, z m and a Boolean variable x that controls the relay coil. We construct switching circuits that are free from the influence of external factors whose indicators are z 1,?, z m .

In this paper, we analyze the performance of two-way amplify-and-forward (AF) relaying with best relay selection scheme in the presence of hardware impairment at the relays. We first obtain the tractable closed-form expression of the statistical characteristics for the end-to-end signal-to-noise ratio (SNR). To reveal significant insights into the system performance, we also computed the asymptotic symbol error probability (SEP), which is shown extremely tight in the high SNR regime and low hardware impairments level. Our analysis enables us to evaluate the impact of non-ideal hardware on the performance of two-way relaying networks and to highlight as a benchmark for system designers.

An improving efficient algorithm for generation of the state equations in full symbolic, partly symbolic or numeric normal-form is presented. This algorithm has been implemented in a program — called SYSEG — SYmbolic State Equation Generation. The program allows the formulation of symbolic state equations without any inverse of a symbolic matrix, and, by cancellation and simplification of the expressions it offers a symbolic compact form. SYSEG program identifies, as type and number, any kind of excess elements, ant it can analyze and design both linear and nonlinear analog circuits. The state equations can be integrated with Matlab routines. Using the state equations in operational form (for the linear and/or piecewise-linear nonlinear analog circuits) the transfer functions in full symbolic, partly symbolic or numeric form are generated. An illustrative example is given to prove that SYSEG program is a very useful tool for symbolic analysis and design of linear and/or nonlinear time-invariant analog circuits.

Summary form only given. We describe the use of symmetry for verification of transistor-level circuits by symbolic trajectory evaluation (STE). We present a new formulation of STE which allows a succinct description of symmetry properties in circuits. Symmetries in circuits are classified as structural symmetries, arising from similarities in circuit structure, data symmetries, arising from similarities in the handling of data values, and mixed structural-data symmetries. We use graph isomorphism testing and symbolic simulation to verify the symmetries in the original circuit. Using conservative approximations, we partition a circuit to expose the symmetries in its components, and construct reduced system models which can be verified efficiently. Introducing X-drivers into switch-level circuits simplifies the task of creating conservative approximations of switch-level circuits. Our empirical results show that exploiting symmetry with conservative approximations can allow one to verify systems several orders of magnitude larger than otherwise possible. We present results of verifying Static Random Access Memory (SRAM) circuits with up to 1.5 million transistors.

Nowadays, the use of electronic control units are limited in applications that require high safety integrity. Therefore, to satisfy the conditions for applications requiring high reliability, control circuits are used instead of digital electronic control units like PLCs. Due to the lack of efficient, simple and applicable methods in the literature, design of control circuits are mainly based on heuristic methods. In this study, existing problems related to the application of the known formal methods will be examined and an effective solution will be proposed.

A new method is proposed for hierarchical symbolic analysis of large analog integrated circuits. It consists of performing symbolic suppression of each subcircuit to its terminals in terms of subcircuit matrix determinants and cofactors, and applying Cramer's rule to symbolically solve the set of equations at the top level of the circuit hierarchy. An annotated, directed, and acyclic graph, called determinant decision diagram (DDD), is used to represent symbolic determinants of subcircuit matrices and cofactors used in subcircuit suppression, as well as symbolic determinants of the top-level circuit matrix and cofactors required in applying Cramer's rule. DDD enables us to systematically exploit the inherent sparsity of circuit matrices and the sharing of symbolic expressions. It is capable of representing a huge number of symbolic product terms in a canonical and highly compact manner. The proposed method is illustrated using a Cauer parameter low-pass filter. It has been implemented in a symbolic analyzer and compared to best-known hierarchical symbolic analyzer SCAPP and numerical simulator SPICE. Experimental results on several analog circuits including the /spl mu/A741 operational amplifier - a circuit with less structural regularities - are described.

This paper describes the laboratory implementation and real-time test results of a new neural network (NN) based digital differential relay used for detecting faults and classifying internal faults in the stator winding of synchronous generators. Details of the software written to enable the operation of the relay are described. Behavior of the NN based relay is observed and the experimental results are presented.

To improve the simulation efficiency of switched circuits, it is advantageous to model their switching devices as short and open circuits. The disadvantage is that such models may cause inconsistent initial conditions (IIC), and Dirac impulses may appear. Conventional simulators do not handle such situations correctly. This paper introduces a new algorithm for analyzing circuits with IIC by a mixed numerical-symbolic method. The method detects the order of the Dirac impulse and also finds the correct initial conditions after switching. It is applicable to nonlinear circuits.

A new method for symbolic behavioral model generation of nonlinear analog circuits is presented. Equation-based simplification techniques for symbolic analysis of nonlinear circuits are proposed. They comprise global and local simplification operations which are performed on the system of nonlinear circuit equations. This system is derived from a transistor level netlist. Behavioral models are generated for DC-transfer and multiple AC operating conditions using an efficient error estimation algorithm. They include symbolic physical circuit parameters and allow deeper insight into nonlinear circuit behavior. Some examples are given to show the feasibility of this approach.

This paper presents, in a constitutive and functional approach, an original, improved performance directional relay which as proved to yield better results as compared to similar devices employed in relay protection circuits The directional relay described here has been designed to insure selectivity in maximal protection circuits for two-end supply networks and in transversal differential double-line protections, as well as to act as a component of long distance safeguarding of interconnected networks and as a protection device to prevent the engine operational status of synchron generators The scheme of the relay is based entirely upon static commutation. The working principle is based on controlling the phase differences between the current and the voltage in the circuit to be safeguarded through an electronic phase detector consisting of integrated circuits. The relay contains new elements as compared to traditionally adopted solutions and brings about certain technical and economical advanta...

A symbolic construction method allowing for parameter limit operation is proposed. Switched-capacitor circuits can be analyzed with this method by creating a symbolic z-domain transfer function represented in the form of a Binary Decision Diagram (BDD). Manipulating the symbols in BDD can simulate a variety of circuit faults, such as switch faults, capacitor faults, and opamp gain faults. Implementation methods are presented and illustration examples are provided.

The main switching block is presented to distinguish the switching behaviors and the degree of the converter's complexity during one switching period. By adopting the coarse-grained symbolic sequence method, the secondary switching block and secondary symbolic sequence are established in terms of main switching block too. Hence the duplicate symbolic sequence is put forward to detect bifurcation types in DC-DC switching converters. A voltage-mode-controlled flyback converter is used as an example to illustrate the applications of the duplicate symbolic sequence.

International audience; This paper presents a new software which can generate in full-symbolic or numeric-symbolic form the Y, Z, H, and fundamental parameters of a two-port structure. Our procedure can also determine all the resonant frequencies of any two-port configuration as functions of the two-port circuit parameters. The procedure is based on the modified nodal equations in full-symbolic form. A new software called ANCSYANP (Analog Circuit Symbolic Analysis Program) was elaborated. This is an interactive tool that combines symbolic and numeric computational techniques, and which uses the facilities of the symbolic simulator Maple to manipulate the symbolic expressions. An illustrative example is done.

In the paper, the problems of design of the parallel space switching systems is considered. The shortcomings of crossbar switches are analyzed as well as the possibilities of design of parallel switching in multistage systems. There is also a description of the structure of parallel cross switch, which is the basic one in building the ladder circuits. The structure of the switching elements of the parallel space switching systems is described as well. The parallel space switching systems based on such switch cabins will allow to reduce the connection time and losses caused by the congestion of the general control unit.

Modeling tools are useful for educational and industrial use. Such tools help the new engineers to simulate the power system under normal and faulty conditions. This paper presents the design and various data conversion steps of a digital negative sequence relay. The digital relay has a superiority over electromechanical relay in terms of accuracy and speed. The detection of negative sequence current and appropriate action is useful for protection of power system components. The operation of relay should be fast and reliable for minimum outage of power system in case of abnormality or electrical fault. In this paper, the relay performance under different system dynamics is also visualized on MATLAB / SIMULINK® considering a 400V power system.

In this paper presents an algorithm for directional over-current relay coordination based on linear programming. The relays are configured by adjusting time dial setting (TDS) of function properly in normal and fault conditions. The TDS adjustment is performed by using linear programming. For test, 6-bus and 9-bus test power systems are situated. Furthermore, there are also identified primary relay and backup relay pairs when fault occurred. Performance above that can solve the problems; adjust TDS of each relay and determine the minimum time relay coordination. The results illustrated that linear programming is simple and can be used for solving optimal coordination of directional over-current relays.

This paper shows how to obtain the capacity of modular additive noise of an arbitrary single-input- single-output (SISO) relay network. The arbitrary SISO relay network is a network where the relays are interconnected with each other in various combinations. Its capacity is obtained by using a quantize-and-forward (QAF) strategy at each relay node. This paper considers all channels as discrete memoryless channels. In order to obtain the capacity of an arbitrary SISO relay network, this paper simplifies the network in terms of a parallel and serial relay network and finds the capacity. First, the capacity expression for a parallel relay network is obtained. In a parallel relay network, the source is transmitted to all relays; then each relay, using a QAF strategy, forwards the source to the destination. Second, the capacity expression for a serial relay network where the relays are interconnected serially is obtained. Finally, after expressing the capacities for parallel and serial relay networks, this paper explains how to obtain the capacity for any arbitrary SISO relay network.

The authors present a symbolic switched capacitor (SC) circuit analysis program, called SSCNAP, which was developed on a microcomputer. The program is based on a method that uses numerical algorithms at all stages. Partially or totally symbolic transfer functions, large-change sensitivities, relative sensitivities, and poles and their sensitivities for arbitrary K-phase SC circuits can be obtained using SSCNAP. No topological or duty-cycle constraints have been imposed on the circuits. The discussion is limited to ideal SC circuits that do not contain any resistances. >

This chapter contains sections titled: Introduction Classification of Techniques for the Symbolic Analysis of SC Circuits Algebraic Methods Circuit Transformation Methods Signal Flowgraph Methods Parameter Extraction Methods Conclusions This chapter contains sections titled: Acknowledgments References

This chapter contains sections titled: [1] A Symbolic Analysis of Relay and Switching Circuits Series-Parallel Realization of the Sum Modulo Two of n Switching Variables [6] Mathematical Theory of the Differential Analyzer [13] The Theory and Design of Linear Differential Equation Machines [14] (With John Riordan) The Number of Two-Terminal Series-Parallel Networks [42] Network Rings [44] A Theorem on Coloring the Lines of a Network [50] The Synthesis of Two-Terminal Switching Circuits [54] Programming a Computer for Playing Chess [55] A Chess-Playing Machine [70] Presentation of a Maze Solving Machine [73] A Mind-Reading (?) Machine [75] The Potentialities of Computers [76] Throbac I [85] (With D. W. Hagelbarger) A Relay Laboratory Outfit for Colleges [93] A Universal Turing Machine with Two Internal States [94] (With Karel de Leeuw, Edward F. Moore and N. Shapiro) Computability by Probabilistic Machines [97] The Simultaneous Synthesis of s Switching Functions of n Variables [99] Game Playing Machines [11] (With Peter Elias and Arniel Feinstein) A Note on the Maximum Flow Through a Network [89] and [90] (With Edward F. Moore) Reliable Circuits Using Less Reliable Relays [114] Von Neumann's Contribution to Automata Theory [120] Computers and Automation?-?Progress and Promise in the Twentieth Century [126] Scientific Aspects of Juggling [5] The Use of the Lakatos-Hickman Relay in a Subscriber Sender [7] A Study of the Deflection Mechanism and Some Results on Rate Finders [8] Backlash in Overdamped Systems [11] Some Experimental Results on the Deflection Mechanism [30] (With C. L. Dolph) The Transient Behavior of a Large Number of Four-Terminal Unilateral Linear Networks Connected in Tandem [7 4] (With E. F. Moore) The Relay Circuit Analyzer [84] (With E. F. Moore) The Relay Circuit Synthesizer References

Shannon in his 1938 Masterpsilas Thesis demonstrated that any Boolean function can be realized by a switching relay circuit, leading to the development of deterministic digital logic. Here, we replace each classical switch with a probabilistic switch (pswitch). We present algorithms for synthesizing circuits closed with a desired probability, including an algorithm that generates optimal size circuits for any binary fraction. We also introduce a new duality property for series-parallel stochastic switching circuits. Finally, we construct a universal probability generator which maps deterministic inputs to arbitrary probabilistic outputs. Potential applications exist in the analysis and design of stochastic networks in biology and engineering.

Transmission line protective relays are assuring normal operation of power system by automatically isolating faulted sections. Different disturbances in power system could affect relay behavior and may result in relay misoperation or unintended operation. This paper explores various aspect of the performance analysis of existing protective relays. Three categories of solutions are discussed: 1) relay performance evaluation based on relay testing; 2) on-line relay monitoring based on advanced fault analysis and relay dynamic performance analysis; 3) intelligent alarm processing based on analysis of the relay logic operands. Case study and benefits are presented for each solution for relay performance analysis to demonstrate the advantages.

The switching cell concept was first introduced and used in order to study the micro-phenomena involved in the switching process; parasitics' influence, switching losses, snubbers, soft switching principle and so on. The authors demonstrate that the switching cell can also be a very efficient tool in the study of various converter topologies. As examples, two soft switching cells that can be used in any DC-DC converter are described. They give the quantitative study and show how the study of a single switching cell leads to a thorough knowledge of a whole set of converters, especially their open loop output characteristics and the design.

In this paper a novel method for circuit analysis is proposed. It is based on using symbolic analysis in matrix form, which is especially appropriate for repetitive similar calculations of the same circuit. The method, which applies hyper-complex numbers (hypernions), was first developed by the authors for analyzing the non-sinusoidal operation of electrical circuits. Now, the method has been extended to the analysis of electronic/switching circuits in which the sources and/or the parameters are step-wisely changed as a result of switching. Such circuits are common in different kinds of DC-DC converters (such as Buck, Boost, Cuk, etc. converters). The proposed method gives a new approach to the analysis of the above circuits by opening the possibility of treating them in a general-analytical form, just like in regular electrical circuits having a constant configuration and constant parameters. The computation of such kinds of circuits by using the proposed method becomes very simple, since the circuit does not have to be analyzed many times, each time for a different configuration, but at once by performing a parallel computation. The theoretical presentation is accompanied by numerical examples.

Interactive simulation and verification SIMULINK models for dc-dc switching converter circuits using pulse-width-modulation (PWM) control ICs are devised in this paper. Although some assumptions are made to simplify the SIMULINK behavior models, the likeness between the simulation and experimental results for both transient and steady-state responses shows that these behavior models capture almost all the important characteristics of the dc-dc switching converter circuits. Therefore, these behavior models can be very good teaching aids for students to learn the differences between ideal circuits and practical implementations. With these SIMULINK behavior models, students can also validate quickly whether or not their designs of feedback controllers for dc-dc switching converter circuits implemented with PWM control ICs meet the prescribed performance requirements.

Power dissipation and reliability are important issues in the design of high performance digital VLSI circuits. Power dissipation and reliability are strongly related to switching activity in the circuit. An estimate of maximum switching activity is necessary for the design of reliable circuits. The problem of estimating maximum switching activity even under a zero gate delay model is intractable. In this paper, we present an algorithm to obtain an upper bound on the maximum transition count over all possible input vectors under a zero gate delay model.

We propose a new method to estimate the delay-dependent switching activities of the combinational circuits. The method extends the transition density in order to handle the delay dependent properties of glitches; each transition density is tagged with its time stamp. It also combines the accurate power estimation of the symbolic simulation under the zero-delay model and the efficient glitch power estimation of the time-stamped transition density method. The experimental results show that our proposed method estimates the delay-dependent switching activities within about 10% error on the average.

Diode switching circuits have been used in conjunction with emitter followers and current switching circuits to evolve a new set of system building blocks. These blocks exhibit typical delays under five millimicroseconds. Diodes cost less and are physically smaller than transistors; therefore, this new system is cheaper and faster than an all-current switching system and permits at least a fivefold increase in packaging density.

THE VALUABLE PROPERTIES of transistors as efficient switching elements are well known and the use of transistors in digital circuits has become widespread. An allied area receiving much less attention is the use of transistors in ac signal switching. This paper discusses the transistor characteristics required for bilateral switching and circuit techniques developed to exploit these characteristics.

In the paper, the problem of searching free connecting ways is discussed. The space-temporary switching units are described and the main structure of the switching system has been described.

The paper develops a state variable approach to model ideal switching in inconsistent initial conditions circuits. The use of ideal circuit elements and ideal switching simplifies the analysis of switched networks, but often leads to circuits with excess storage elements and with inconsistent initial conditions. In such cases, a joint change in the state of a set of switches brings the circuit in different states, for the same state before the switching, depending of the ordering of the individual events that compose the multiple switching, even when the total duration of the switching vanishes.

A formulation approach for symbolic analysis of analog circuits modeled by nullors, is introduced. The proposed technique is based on manipulating data-structures: including only admittances, nullators and norators, instead of the nodal-admittance-matrix manipulation. By using this technique, CPU-time minimization as well as fast manipulation of complex symbolic expressions are tasks highly improved. Thus, the reduced system of equations is formulated by fill-in the reduced admittance-matrix using the nullor interconnection-properties.

This paper presents a new method for hierarchical analysis of large circuits that combine numeric and symbolic simulation. Symbolic analysis is applied only on subcircuits at the lowest hierarchical level. This approach proves beneficial for symbolic and numeric simulation. The time reduction is given on a benchmark example.

This paper is intended to show the possibility of performing fault location and identification in the case of single or double faults in analog circuits with a symbolic algorithm that allows using few observable points. A group of test equations, obtained from the symbolic solution of the circuit, is cyclically solved in turn for each group of parameters under test, leaving the other ones at their rated value. A validation equation, still obtained from the same symbolic solution, has the task of validating the faulty or non-faulty situation for those parameters.