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Fox News is one of the most popular news sources in the United States. Yet, there are those who reject the idea that Fox should be considered a news source in the first place, claiming it should be considered something more akin to propaganda. This article uses the ambiguity surrounding Fox News’ classification as an opportunity to explore how news sources get defined and categorized within journalism research and practice. It discusses three approaches that can be utilized to understand and categorize partisan media—producer-focused, audience-focused, and critical/normative. It explores the benefits and limitations of these perspectives and the need for scholarly inquiry that transverses and synthesizes them. We argue that an increasingly variegated news landscape calls for scholars to develop a richer vocabulary for distinguishing key features of partisan news outlets and greater reflexivity in research design that acknowledges the challenges inherent in translating meaning and values between producers, audiences, and scholars.

This essay reviews two new books examining different aspects of right-wing humor, “The Souls of White Jokes” (Stanford University Press, 2022) by Raúl Pérez and “That’s Not Funny” (University of California Press, 2022) by Matt Sienkiewicz and Nick Marx. It puts these works into conversation with a longer tendency within right-wing studies to focus on media content and motivations within a negative affective range. By focusing on the positive emotions associated with white supremacy and right-wing media, these books mark an important turning point away from reductionist accounts of the “reactionary mind” and toward a fuller understanding of the complex and contingent motivations of conservatives.

An analytical tool to design 4H-SiC power vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect-Transistor is proposed. The model optimizes, in terms of the doping concentration in the Drift–region, the trade–off between the ON–resistance, RON, and the maximum blocking voltage, VBL, that is the Drain-Source voltage for which the avalanche breakdown appears at the p+–well/n-DRIFT junction together with the breakdown of the Gate oxide. Finding such trade-off means to maximize, Figure-Of-Merit. Our results are based on a novel full–analytical model of the electric field in the Gate oxide, EOX, whose generality is ensured by the absence of fitting and empirical parameters. Model results are successfully compared with 2D–simulations covering a wide range of device performances.

Point contact current voltage (PCIV) measurements were performed on 4H-SiC samples, both for n- an p-doped epitaxial layers as well as samples with rather shallow doping profiles realized by N- or Al-implantation in a range from 1016 cm-3 to 1019 cm-3. Surface preparation and measurement parameters were investigated in order to determine their influence on the measured resistance profiles. Furthermore depth profile measurements were performed on both an epitaxial layer as well as on implanted samples. These depth profiles could be measured reproducibly and showed good agreement with expected profiles for Al-implanted samples as well as for epitaxial layer whereas for N-implanted samples deviations between measured and expected profiles could be observed. It could be proven that PCIV profiling technique is a promising method for characterizing doped profiles in 4H-SiC, especially on Al-implanted samples.

In this study, the basic device features of a novel monolithically integrated solid-state-circuit-breaker (MI-SSCB) are demonstrated and analyzed using numerical simulations. Thereby, the MI-SSCB is built according to the concept of the dual thyristor. But, in comparison to similar technical solutions reported in literature, due to the advanced device structure proposed in this study a monolithically integration could be achieved for the first time.

In this work, the feasibility of the Bipolar-Injection Field Effect-Transistor (BIFET) [5] in two different Dual Thyristor type circuits [4] for an application as solid-state circuit breaker (SSCB) is experimentally verified. The Dual Thyristor type circuits are assembled from discrete silicon JFETs and a silicon carbide BIFET and are electrically characterized at various temperatures. The current-voltage characteristic shows the expected regenerative self-triggered turn-off capability under over-currents and the option to control the turn-off current by a passive resistor network. The issue with the adverse positive temperature coefficient of the trigger-current can be solved by putting the SiC BIFET in a cascode arrangement with a silicon Dual Thyristor. In this configuration the SiC BIFET provides the high voltage blocking capability and the silicon Dual Thyristor with its negative temperature coefficient controls the trigger-current. Transient analyses of both circuits indicate fast switching times of less than 50 μs seconds. It is demonstrated for the first time, that the SiC BIFET, due to its normally-on behaviour, used in a Dual Thyristor type circuit is a promising concept for self-triggered fuses in high current and high voltage applications.

In this article, we report the experimental results of a visible-light-blind 4H-polytype silicon carbide phototransistor able to detect ultraviolet (UV) radiations for wavelengths lower than 380 nm with a significative improvement in the optical gain compared with the state-of-the-art of 4H-SiC UV phototransistors. From the electro-optical measurements, the device shows a dark current of 0.62 pA, an ON-/OFF-current ratio of seven orders of magnitude up to bias voltage of −0.5 V, and an excellent optical gain of $1.14\cdot {10}^{{{5}}}$ at 300 nm, whereas it is only $2.6\cdot {10}^{-{{3}}}$ at 400 nm demonstrating a good rejection of visible radiations. Besides having high optical gain, the phototransistor is also more sensitive than the conventional 4H-SiC UV detectors for wavelengths with low penetration depths, because its structure is designed to have the electric field up to the radiated surface where the photogenerated electron–hole pairs are efficiently swept up before recombination occurs. The operating principle of the detector is also investigated, and we experimentally proved that differently from the conventional 4H-SiC bipolar junction transistor phototransistor, it is based on the change in the potential barrier height, which controls the current flow, due to the variation in the Fermi levels when the electron–hole pairs are photogenerated. A comparison with the state-of-the-art of 4H-SiC UV phototransistors is reported.

The influence of oxidation pulse during atomic layer deposition (ALD) process on electrical and dielectric properties of metal–insulator–metal (MIM) structures with different ZrO 2 -based (e.g. pure ZrO 2 , Al- and Si- doped ZrO 2 ) high- k dielectrics and different thicknesses has been investigated. Strongly pulse-time dependent as well as independent phenomena are observed and their thorough analysis has given more insight on the processes taking place in these structures thus allowing further optimization of their electrical performance. Longer oxidation pulses produce films with larger thicknesses which may be related to the incorporation of excess oxygen in the layers and the formation of less dense films. Incorporation of Al and 10 s pulse time are the most beneficial and provide structures with the lowest leakage current. At high positive voltages a significant increase of current and a change of I – V curve shape with increasing pulse time have been observed. The possible processes which provoke this change have been discussed. The analysis of leakage current mechanisms reveals that neither incorporation of Al or Si in ZrO 2 nor oxidation pulse time change the energy position of traps participating in the conduction process, hence the nature of these traps remains unaffected – it is a single positively charged oxygen vacancy in ZrO 2 . The oxidation pulse time of 5–10 s is the optimal one which provides structures fulfilling the requirements for next generation MIM-based dynamic random access memories (DRAMs).

Metal-insulator-semiconductor capacitors used as a RC snubber attenuate voltage overshoots which may occur during switching phases. These devices feature good temperature stability up to 200°C and can be integrated very close to power switches on the same transfer substrate. As the capacitors need to withstand high voltages in most applications, thick dielectric layers have to be used, causing significant amount of wafer bow during processing. A dielectric stress compensation structure on the back side of the wafers is therefore introduced and shown to reduce the resulting wafer bow by up to 50%. Planar MIS capacitors using a 1 μm thick dielectric layer stack achieve dielectric breakdown voltages of up to 1000 V along with capacitance densities of 5.4 nF/cm2. In comparison, devices with a dielectric layer thickness of 250 nm exhibit a capacitance density of 13.6 nF/cm2 and a resulting dielectric breakdown voltage of 250 V.

In this study, we present results on electrical characterization of bipolar pn-diodes to investigate the temperature and electrical field dependent behavior of ambipolar mobility in n-doped 4H-SiC. Therefore, static current-voltage measurements to calculate the specific differential resistance and dynamical reverse recovery measurements to determine the mean carrier concentration were carried out for different temperatures and forward current densities. The specific differential resistance of the drift layer decreased from 10 mΩcm2 at 80 Acm-2 to 6.6 mΩcm2 at 180 Acm-2, whereas the mean carrier concentration only increased from 4.1015 cm-3 to 8.1015 cm-3, indicating a decreasing ambipolar mobility. The calculated reduction of the ambipolar mobility from 800 cm2V-1s-1 to 650 cm2V-1s-1 in dependence on the current density has to be attributed to an increasing electric field from 150 Vcm-1 to 250 Vcm-1 and increasing carrier scattering due to higher carrier concentrations. For example, at a constant conduction current density of 160 Acm-2, the ambipolar mobility decreases from 710 cm2V-1s-1 at 300 K to 650 cm2V-1s-1 at 450 K.

Graphical abstractDisplay Omitted The origin of the TDDB bimodality was studied in high-k (HK) gate stacks using a CAFM.The roles of the interfacial layer/HK layer and the HfO2 polycrystalline structure were evaluated.Bimodal characteristic was attributed to the different electrical properties of Gs and GBs.BD preferentially occurs in the interfacial SiO2 (IL) layer beneath the GBs.The gate stack BD is triggered by the BD of the SiO2 layer. Dielectric breakdown (BD) in polycrystalline HfO2/SiO2 gate stacks has been studied using a conductive atomic force microscopy (CAFM) technique, which allows employing a nanosize probe to apply a highly localized electrical stress. The resulting BD statistics indicate that BD preferentially occurs in the interfacial SiO2 (IL) layer beneath the grain boundaries (GBs) of the overlaying polycrystalline HfO2 film due to higher conductivity of the GB compared to that of the grains.

In this study, we present the results of alloying nickel as ohmic contact material to n-type 4H-SiC via a continuous wave fiber laser with different laser beam powers and processing times. The laser system exhibits an emitting wavelength of 1070 nm and a beam propagation factor M2 smaller than 1.1. Contact resistance was determined by current-voltage measurement using the two-terminal contact resistance method. The results indicate that a laser beam power of at least 100 W is mandatory to initialize contact silicidation. Although the contact resistance is improvable by longer processing times, our experiments outline the much higher impact of laser beam power to contact silicidation compared with processing time. For laser beam powers of 300 W and processing times of 0.5 s a contact resistance of 6.5 , comparable to contacts alloyed in a lamp heated furnace at 910 °C for 2 min with a contact resistance of 10.3 , was achieved.

Passive snubber networks are especially needed in fast switching power modules to prevent overvoltage from hard switching and to minimize electromagnetic interference [1]. In a half-bridge circuit as shown in Fig. 1 (a) dissipative RC snubber networks are beneficial over single pulse capacitors as they do not generate a resonant pole in the impedance spectrum, which can be seen in Fig. 1 (b). As only a small capacitance (e.g. 4 nF) is needed to reduce the overvoltage (Fig. 1 (c)), a monolithically integrated RC snubber can be realized on a silicon chip and packaged directly on the power module substrate. An improved module performance was already demonstrated for chip snubbers with 200 V operating voltage [2]. This work shows how the device design was enhanced for high manufacturability and reliable operations in a voltage range from 600 V to 900 V.

Anti-fuse devices based on non-volatile memory cells and suitable for power electronic applications are demonstrated for the first time using silicon technology. These devices may be applied as stand alone devices or integrated using standard junction-isolation into application-specific and smart-power integrated circuits. The on-resistance of such devices can be permanently switched by nine orders of magnitude by triggering the anti-fuse with a positive voltage pulse. Extrapolation of measurement data and 2D TCAD process and device simulations indicate that 20 A anti-fuses with 10 mΩ can be reliably fabricated in 0.35 μm technology with a footprint of 2.5 mm 2 . Moreover, this concept offers distinguished added-values compared to existing mechanical relays, e.g. pre-test, temporary and permanent reset functions, gradual turn-on mode, non-volatility, and extendibility to high voltage capability.

In this work we present 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) with a stable protective coating for harsh environment applications. Both inversion channel (IC) and buried channel (BC) MOSFETs were realized on n-4H-SiC substrates with a p-epilayer. Stacked ONO gate dielectric and Ti/TiN/Pt/Ti interconnect were used. Ni and Ti ohmic contacts in combination with a-SiOx/a-SiNy and a-SiOx/a-SiC protective coatings were compared. The MOSFETs showed excellent transistor characteristics up to 600 °C and exceptional stability during long-term aging at 600 °C in air and during accelerated aging at 700 °C including temperature cycling and air/moisture environment.

Scanning probe microscopy techniques and, in particular, scanning spreading resistance microscopy (SSRM) were used for a detailed characterization of focused ion beam (FIB) induced damage in the surrounding of purposely irradiated areas on silicon. It is shown that the damaged area detected using these techniques extends up to several micrometers around the irradiated structures. The influence of the key FIB processing parameters on the FIB induced damage was examined. Parameters which were taken into account are the ion dose (from 1012 to 1018 cm−2), the milled structure size (circle diameters from 0.25 to 10 µm), the beam energy (from 10 to 30 keV), and the beam current (from 1.5 to 280 pA). Moreover, the influence of the SSRM settings on the measurement results was investigate d. Settings which were considered are the bias voltage and the force applied to the tip during the SSRM analysis. High resolution transmission electron microscopy and secondary ion mass spectroscopy analyses were performed to validate the SSRM results. Scattering between Ga ions and residual gas particles in the vacuum chamber of the FIB tool is identified as the main reason for the observed damaged area.

A novel average inductor current sensing circuit integrable in CMOS technologies is presented. It is designed for DC---DC converters using buck, boost, or buck-boost topologies and operating in continuous conduction mode at high switching frequencies. The average inductor current value is used by the DC---DC controllers to increase the light load power conversion efficiency (e.g., selection of the modulation mode, selection of the dynamic width of the transistors). It can also be used to perform the constant current charging phase when charging lithium-ion batteries, or to simply detect overcurrent faults. The proposed average inductor current sensing method is based on the lossless sensing MOSFET principle widely used in monolithic CMOS integrated DC---DC converters for measuring the current flowing through the power switches. It consists of taking a sample of the current flowing through the power switches at a specific point in time during each energizing and de-energizing cycle of the inductor. By controlling precisely the point in time at which this sample is taken, the average inductor current value can be sensed directly. The circuit simulations were done with the Cadence Spectre simulator. The improvements compared to the basic sensing MOSFET principle are a lower power consumption because no high bandwidth amplifier is required, and less noise emission because the sensing MOSFET is no more switched. Additionally, the novel average inductor current sensing circuit overcomes the low bandwidth limitation previously associated with the sensing MOSFET principle, thus enabling it to be used in DC---DC converters operating at switching frequencies up to 10 MHz and above.

In this work, the DC-arc behavior of an active fuse integrated into a CMOS process is described. The purpose of this fuse is to prevent serious hazards in power electronics in the case of a malfunction of a single power-transistor. The focus of this work is on the characterization of functionality and reliability of the “cutout-bridge”. Different cutout-bridge geometries and the DC-arc behavior during fuse release are analyzed. It is shown that a significant increase in release time occurs, when a DC-arc across the cutout-bridge is ignited at voltages above 20 V. By integrating a snubber device into the circuit, the DC-arc behavior will be clearly reduced and the release time of the fuse will be decreased significantly.

In this paper the tuning of the n-metal effective work function by implantation of lanthanum is demonstrated. The effect of implantation and thermal annealing on the device flat-band voltage is presented. It is shown that lanthanum doping of the gate stack produces a negative shift of the flat-band voltage of -0.53 V for a lanthanum does of 5x10^1^4 cm^-^2, after the device undergoes S/D anneal conditions. The results are discussed within the framework of a phenomenological dipole model and compared with other results

The use of hafnium silicate (HfSiO) as a charge trapping layer in charge-based non-volatile memory cells will be discussed. First, fundamental properties (e.g., dielectric constant, trap depths/levels) of the hafnium silicate layers, deposited from a single-source precursor, are deduced from capacitance–voltage and current density–voltage measurements. The oxide trap density of the analyzed HfSiO layers can be tuned to exceed that of silicon nitride. At the same time, a significant reduction of the write voltage is achieved due to a reduced effective oxide thickness. The erase operation, however, is hampered by the lower electric field at the HfSiO layer due to its high dielectric constant. Measurements also indicate that HfSiO exposed to a higher thermal budget during device fabrication results in fewer trapping centers. Retention measurements show that information can be reliably stored in memory cells with a trapping layer of HfSiO for more than 10 years similar to their silicon nitride counterparts. But the thickness of the top and bottom oxides must be increased for compensation of additional charge losses which are due to lower trap depth and free electron mass in HfSiO.

High-voltage 4H-SiC Junction Barrier Schottky diodes with a reverse breakdown voltage of over 4.5 kV and a turn-on voltage below 1 V have been fabricated. They achieved a forward current of 5 A at a forward voltage drop of 1.8 V and 20 A at 4.2 V. A low reverse leakage current of 0.3 μA at 1.2 kV and 37 μA at 3.3 kV was measured. The chip size was 7.3 mm x 7.3 mm, the active area 0.25 cm2 and the diode was able to handle a repetitive pulse current density of over 300 A/cm2 without degradation. Floating field rings in combination with a field-stop ring were used as edge termination to reach 73 % of the theoretical breakdown voltage. The epitaxial layer was 32 μm thick, with a nitrogen doping concentration of 1 x 1015 cm-3. The JBS diodes have been manufactured in a 100 mm SiC prototyping line, using well established processing technology, to achieve cost-efficient devices.

SONOS-type MIS capacitors with hafnium silicate as a control oxide are characterized and compared to devices featuring a conventional SONOS gate stack. Write operation is comparable for both gate stack types. Erase operation for the devices with hafnium silicate is improved since the parasitic injection of electrons from the gate is suppressed due to the low electric field in the high-k material. This reduction in leakage current through the gate enhances oxide stability. However, measurements indicate that charge retention for the gate stack with hafnium silicate is degraded for high charge densities. Band bending of the control oxide under high electric fields increases the tunneling probability for trapped charges. Additionally, initial flatband voltage decay is observed due to charge trapping in the hafnium silicate layer. Reducing the thickness of the hafnium silicate layer is possible, maintaining favorable erase properties while minimizing the charge decay rate during retention.

In this work, hafnium silicate layers on Si and Ge wafers for gate dielectric application in metal–oxide–semiconductor devices are investigated. Films are deposited by metal–organic (MO)CVD using the single-source precursor Hf(acac)2(OSitBuMe2)2. This precursor exhibits good properties in terms of hydrolysis stability, volatility, and deposition. However, precursor decomposition is affected by surface conditions. Films deposited on Si wafers reveal high C contamination (up to 20 at %) and low Si content (up to 20 at %). In contrast, for film deposition on Ge wafers, no C contamination can be detected and Si incorporation is delayed until after about 15 nm HfO2 dielectric growth. Post-deposition rapid thermal annealing in an O2 atmosphere causes crystallization of deposited films, Si and Ge redistribution in the dielectric, respectively, and interfacial layer growth. However, oxygen annealing was also found to reduce effective oxide thickness (EOT) significantly compared to as-deposited films, which is attributed to crystallization effects. However, scaling of EOT is limited by that interfacial layer growth. Leakage currents are mainly caused by trap-related conduction mechanisms. Energy levels of involved traps decrease with increasing crystallization and/or Hf content, and values of 0.5 eV and 1 eV related to Hf and Si bonds, respectively, are obtained.

In this work, silicon insulator interfaces are characterized by detailed photocurrent analysis. Results obtained for a variety of samples with different insulator layers and layer thicknesses are presented and discussed. The results show the applicability of the technique for a reliable process control and include data on high-k layers for the first time. Comparison of experiment and simulation is used to explain the injection level dependence of the measurements.

For future technology generations, the replacement of silicon dioxide as gate dielectric in metal-oxide semiconductor devices becomes a challenging issue. Metal silicates are promising candidates in this context. In this paper, the potential of zirconium silicate films obtained by metal-organic chemical vapor deposition from a novel single-source precursor is shown. On basis of metal insulator semiconductor capacitors, data from capacitance-voltage, current-voltage, constant voltage stress, and constant current stress measurements are presented. Detected charge trapping phenomena, conduction mechanisms, and polarity dependence of device degradation are discussed.

The potential of zirconium silicate films as an alternative gate dielectric to silicon oxide in future technology generations is demonstrated. Novel single-source precursors for metal organic chemical vapor deposition (MOCVD) of zirconium silicate films are presented. These precursors meet the demands for implementation in a MOCVD process in respect to purity, volatility, and deposition temperature. Zirconium silicate layers were deposited and metal insulator semiconductor capacitors were manufactured. Structural characterization of the films was performed by means of X-ray photoelectron spectroscopy, secondary neutral mass spectroscopy, transmission electron microscopy, and ellipsometry. It was found that the silicon content in the zirconium silicate films is less than stoichiometric and carbon free films can only be obtained at deposition temperatures above 550 °C. The permittivity of the films is about 10.5–15. Electrical characterization by capacitance as a functions of voltage and current as a function of voltage measurement techniques show very promising results: low leakage current (5 × 10 −9 A/cm 2 at −3 V), low level of bulk charge (5 to 6 × 10 11 cm −2 ), and small hysteresis (about 50 mV) were obtained. However, some instabilities, i.e negative charge trapping (up to 2 × 10 12 cm −2 ) during electrical stress, have also been encountered and further investigations should aim at reducing this charge trapping.

Thin films with a considerably higher dielectric constant than silicon dioxide, for example titanium dioxide or titanium containing barium strontium titanate, can be used for dielectrics in ultralarge scale integration devices. TiO2 shows, besides its high dielectric constant, a sufficiently low leakage current and high breakdown field strength. MOCVD is the most promising method for depositing those dielectrics because of its obvious advantages like homogeneity of films, good step coverage and ultrathin film deposition. In this work, three new precursor chemicals have been developed and tested in a low pressure horizontal cold wall-type furnace. For the synthesis of the novel precursors, commercial titaniumisopropylate is brought to an reaction with an alcoholic compound at 150 °C and distilled under vacuum. The motivation for the development of new Ti precursors lies in an improvement of the handling and deposition characteristics as for example the hydrolytic stability. For the three precursors the deposition parameters temperature, pressure, gas flow and activation energy is presented. The electrical properties dielectric constant and leakage current were compared to commercially available titaniumisopropylate.

In this work, we investigate the impact of Al-implantation into n-MOSFET channel regions together with its p-doping concentration upon the mobility limiting scattering mechanisms in the channel. For this purpose, a study of the interface trap density, interface trapped charge density, field-effect mobility, and Hall mobility is carried out for normally-off n-MOSFETs with different doping profiles and concentrations in the channel region. The trend of the field-effect and the Hall mobility as well as the differences thereof will be discussed. Based on the determined mobilities in the range from 11.9 cm2/Vs to 92.4 cm2/Vs, it will be shown that for p-doping concentrations above 5·1016 cm-3 Coulomb scattering is the dominant scattering mechanism for both, low- and high-field mobility. In contrast, for p-doping concentrations below 5·1016, cm-3 further scattering mechanisms will be considered that may account for the observed mobility trend at high electric fields.

Pediatric thyroid diseases cover a large spectrum of congenital and acquired forms, ranging from congenital primary or central hypothyroidism, autoimmune thyroid disease, iodine deficiency, rare genetic defects of thyroid hormone action, metabolism and cell membrane transport to benign nodules and malignant tumors. The previous 15 papers of the textbook Paediatric Thyroidology gave a systematic overview of the current knowledge and guidelines on all these diseases. In this final paper, the authors collected a series of patient histories from their clinics illustrating frequently encountered clinical problems and providing key learning points and references to each case. Although not fully comprehensive, it aims at providing relevant clinical knowledge on thyroid diseases of the neonate, the child, and the adolescent.

Thin silicon oxide nitridation in N 2 0 has been demonstrated to improve the dielectric characteristics in terms of charge to breakdown and trapping under current injection. For the first time we report fairly extensive experimental results of the thermal N 2 0 oxidation of silicon at low pressure. The results clearly indicate a higher oxidation rate in N 2 0 atmosphere than in 0 2 atmosphere at a pressure of 4.5 Torr, in contrast to the rates at atmospheric pressure. Ultrathin (

Effect of a shallow nitrogen implantation in the channel region of n-channel 4H-SiC Hall bar MOSFETs on their electrical properties has been characterized by Hall effect. A significant improvement of Hall mobility in normally-off devices is observed with increasing nitrogen implantation dose up to 1013cm-2with a peak Hall mobility of 42.4 cm2.V-1.s-1. Coulomb scattering as dominant scattering mechanism up to room temperature is demonstrated using temperature dependent MOS-Hall effect characterization.

Ultrathin (less than 10 nm) dielectric films for the application in metal-oxide-semiconductor (MOS) devices have been fabricated in a O2:N2O atmosphere using rapid thermal processing (RTP). It will be shown that with increasing N2O-content in the mixtures of N2O and O2 the oxide thickness decreases and the interfacial nitrogen concentration increases. Therefore, the nitrogen concentration at the Si/SiO2 interface, responsible for improved electrical characteristics, is adjustable by the O2:N2O ratio. High charge-to-breakdown (Q(sub)BD) values comparable to oxides processed in pure N2O atmosphere are obtained for electron injection from the Si-substrate. For electron injection from the gate, the Q(sub)BD-values are considerably higher. For a O2:N2O ratio of 3:1 the highest Q(sub)BD-values have been obtained together with a very homogeneous Q(sub)BD-distribution across the wafer.

Monolithic integration of RC snubbers in power electronic applications offers great opportunities. The presented devices provide tight tolerances and enable high integration densities. Especially, the incorporation into power modules enables reduction of electromagnetic interferences in accordance with reliable lifetime predictions.

A concept for the integration of intermitted trench gates into silicon lateral double-diffused metal-oxide-semiconductor (LDMOS) devices is proposed to achieve a significant reduction in on-resistance. The trench structure can be feasibly integrated into smart-power integrated circuit technology. Using 2-D technology computer aided design (TCAD) simulations, the achievable reduction in $R_{DS, {rm on}}$ from 145 $hbox{m}Omegacdot hbox{mm}{2}$ down to 94 $hbox{m}Omegacdothbox{mm}{2}$ for a 50 V LDMOS device and the negligible impact on the blocking characteristics were demonstrated. Additionally, the device parameters were analyzed with respect to static and dynamic power dissipation. Here, the benefits of trench gate integration became more apparent. Analyzing power losses during high-frequency operation revealed that the increased input capacitance resulting from the trench gate is acceptable for applications where high switching frequencies in the upper megahertz range are not required.

In this work, we present a monolithic RC-snubber for power electronic applications that outperforms state of the art RC-snubbers in terms of characteristic electrical parameters. The principle device structure as well as the process technology is presented. The outstanding properties of the device are a high capacitance per area (1.5 nF/mm2), a low temperature coefficient of the capacitance value (85 ppm/°C) and a low leakage current (

The electrical properties of nanostructured silicon electrodes in contact with phosphate buffered saline were examined using small signal impedance together with cyclic voltammetry. The highest electrode impedance appears at thermodynamic equilibrium, i.e. at zero current potential. Biasing the electrode in both directions decreases the magnitude of the electrode impedance without showing a clear rectifier effect within ± 3V. The impact of nanostructures on the electrode impedance was negligible given the variability between single electrodes.

A dual-layer silicon oxide consisting of reoxidized low-pressure thermal oxide and chemically vapour deposited high temperature oxide at a low pressure prepared by an intra-chamber process is introduced. In this paper, electrical properties of these stacked oxide films are studied. They exhibit higher breakdown field strengths, better charge-to-breakdown characteristics as well as lower defect densities than conventional thermal oxides. Furthermore they reveal low interface state densities and good interface stability under constant current stress. Applying the Fowler-Nordheim tunnelling experiments, the barrier heights between the silicon substrate and the low-pressure oxide and between the metallization and the high-temperature oxide was determined to be 2.8±0.1 eV and 2.6±0.1 eV respectively.

The electrical properties of thin dual-layer silicon oxide films have been studied. These stacked oxide films consist of reoxidized low pressure thermal oxide, and at low pressure, chemically vapor-deposited high temperature oxide prepared by an intra-chamber process without breaking the vacuum. Analysis of these dual-layer oxides reveals lower defect densities as well as higher breakdown field strengths and better charge-to-breakdown characteristics than conventionally produced dual-layer or thermal oxides. Interface quality and stability cannot be improved by stacking silicon oxide films.

A significant improvement of the light load conversion efficiency in integrated CMOS DC---DC converters using pulse-width modulation (PWM) at constant switching frequencies above 1 MHz can be obtained by implementing dynamic width controlling (DWC) of the power transistors. The parallel implementation of DWC uses equally sized power cells, each containing the power transistor and its gate driver stages. The power cells are connected together in a parallel arrangement to limit the propagation delays and to avoid the transmission gates used in serial implementations. Due to this, higher switching frequencies can be realized. Advanced simulations were performed with Cadence Spectre combined with Mathematica to investigate the conversion efficiency improvement potential offered by DWC. With DWC, an absolute increase of the light load conversion efficiency as high as 29% can be achieved for switching frequencies in the range 1---10 MHz. Further, a conversion efficiency higher than 80% can be provided over roughly two decades of load current for a DC---DC converter operating at a switching frequency of 10 MHz. Experimental results obtained from a synchronous buck converter designed in a 0.18 μm CMOS technology and switched at 2 MHz in continuous conduction mode (CCM) have demonstrated an improvement of the light-load conversion efficiency of about 25%.

In this work, we introduce a high voltage 3D-capacitor as a novel passive power device for a 400V application. This device is realized in silicon technology which allows high process reproducibility, high accuracy in capacitance values, and high quality of the dielectric layers (i.e., endurance at high electric field strengths). It can be manufactured discrete or as part of a monolithic integrated circuit. The outstanding properties of the device are a high ratio of capacitance value to consumed silicon area (capacitance enlargement of more than a factor of 16 in comparison to plane capacitors) and very stable capacitance values over a broad temperature range (i.e., average of 24ppm/°C from 20–175°C).

In this work, new results on an active fuse which is a novel power device to prevent serious hazards in power electronics in the case of a malfunction are presented. The focus of this work is on the characterization of the ldquocutout-bridgerdquo in terms of functionality and reliability. Different cutout-bridge geometries and the dc-arc behavior during fuse release is analyzed and by utilizing an additional snubber circuit to minimize the dc-arc behavior, the release time of the fuse was reduced significantly.

In this work, we introduce a high voltage 3D-capacitor as a novel passive power device for a 400 V application. This device is realized in silicon technology which allows process reproducibility, high accuracy in capacitance values, and high quality of the dielectric layers (i.e., endurance at high electric field strengths). It can be manufactured discrete or as part of a monolithic integrated circuit. The outstanding properties of the device are a high ratio of capacitance value to consumed silicon area (capacitance enlargement of more than a factor of 16 in comparison to plane capacitors) and very stable capacitance values over a broad temperature range (i.e., average of 24 ppm/degC from 20-175degC).

In this paper, reliability aspects of thin Zr- and Hf-silicate layers are addressed by analyzing the stress induced leakage current (SILC) and charge trapping during constant voltage stress (CVS) and constant current stress (CCS). Voltage polarity and temperature effects on the degradation of the layers are also studied. SILC is found to have a transient component and its recovery is explained by the trapping/detrapping of traps participating in Poole-Frenkel conduction

In this work, we propose an insulated gate bipolar transistor (IGBT) with a novel lateral triple trench gate architecture, which shows a four times higher forward conduction current compared to devices with a lateral gate or single trench gate structure. For the proof of concept, we realized single trench gate IGBTs using the reduced surface field (RESURF) principle [J.A. Appels, H.M.J. Vaes, A.W. Ludikhuize] for 600V net applications. Typical applications for those integrated smart power systems are, for example, power management of compact fluorescent lamps (CFL) or solid state relays. Further improvement of the forward conduction mode by using triple trench gate structures was studied

We have investigated electrical behaviour of high-k Hf/sub x/Ti/sub y/Si/sub z/O layers with different Hf:Ti ratios in the film. The films are prepared by MOCVD using novel single-source precursors. Oxide and interface charges, leakage currents and conduction mechanisms are found to be a strong function of the film composition. The films with lower Hf content show lower level of oxide and interface charges and higher dielectric constant whereas those with higher Hf content have better leakage current properties. It is established that in the films with lower Hf content the conduction is governed by a phonon-assisted process, i.e. it is defined rather by the intrinsic properties of the layer than by its defect structure.