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This paper presents four topologies of voltage-mode un-terminated IO cells in 28-nm CMOS for singleended rail-to-rail signaling over a passive interposer die in 2.5D configuration for >1Gbps data rates. The presented design explores the existing IO design-space from a 2.5D viewpoint, optimizing existing topologies from area, speed, power and protection perspectives, with a higher degree of configurability in the form of pre-emphasis and slew-rate control. The transmitter (TX) embeds pre-emphasis to enhance high-frequency components of the signal for longer low-pass natured channels. The TX also implements slew-rate control to minimize reflections on shorter channels because of impedance discontinuities and also to minimize simultaneous switching noise. Level-shifting capability embedded in the receiver (RX) enables multi-technology interfacing where different dies are signaling at their core voltages (range: 0.7V-1.8 V) instead of following a particular signaling standard. The measurement results of the transceivers, over a interposer of length of 3.5 mm, demonstrate ±5% duty-cycle distortion with 700 µW at 500 MHz/0.8-V-signaling on the channel with jitter of 20 ps, ±10% duty-cycle distortion with 1.8mW at 1Gbps/0.9-V signaling with jitter of 20 ps, ±10% duty-cycle distortion with 2mWat 2Gbps/0.7-V signaling for 1-V receiver core voltage with a jitter of 10 ps. [ABSTRACT FROM AUTHOR]