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This paper presents a quad-lane serial transceiver that supports virtually all data center communication standards around 8.5–13 Gbps, implemented in 28 nm CMOS technology. The transmitter consists of 20:2 mux followed by a half-rate source-series terminated (SST) driver embedded with a 4 tap FFE and an analog equalizer. The receiver has an adaptive CTLE, 5 tap DFE, and fully digital CDR followed by 2:20 demux. At 13 Gbps, the transceiver can equalize 35 dB Nyquist loss at BER of 10-12. At 1.0 V supply, the transceiver consumes 49 mW/lane at 13 Gbps rate with full equalization capability. An LC VCO-based fractional PLL provides the clocking to quad TX/RX lanes using a low-power inductively tuned clock routing channel. The transceiver architecture not only enables the baud rate operation from 8.5 to 13 Gbps but also supports a wide range of oversampled subrates. This work represents the lowest reported power in its class to date, and the transceiver is suitable for many applications due to its comprehensive flexibility and power efficiency.

This paper presents the design of a power- and area-efficient, high-performance dual-path receiver analog front-end (AFE) for wide multistandard applications of 8.5–11.5 Gb/s, such as 10GBASE-LRM, 10GBASE-KR, 10GBASE-CX1, and 10GBASE-LR/SR. A common programmable gain amplifier (PGA) with programmable peaking is followed by ADC-based and slicer-based paths. The ADC-based path employs a low-power, 6-bit 10 Gs/s, 4X time-interleaved, low BER rectified flash 10 Gs/s ADC that is digitally calibrated to compensate for offset, gain, and phase mismatches between the interleaved channels. The ADC-based receiver with transmitter can compensate for up to a 34 dB insertion loss at 5 GHz Nyquist frequency for a copper backplane channel (10GBASE-KR). The ADC-based receiver can achieve greater than 6 dB margin for three 10GBASE-LRM stressors and dynamic channels. The ADC Figure of Merit (FoM) is a 0.59 pJ/conversion-step for a 5 GHz input at a 10.3125 GHz clock rate. The slicer-based path uses a continuous-time linear equalizer (CTLE) after high linear PGA to provide 10 dB total equalization at 5 GHz Nyquist frequency for 10GBASE-SR application. Its measured input sensitivity of 30 mVppd and high-frequency jitter tolerance of 0.35 UIpp with 0.7 UIpp total input jitter well exceed specifications in the standard. The receiver AFE occupies 0.82 mm 2 and consumes 195 mW for ADC path and 55 mW for slicer path in a 40 nm standard CMOS process.

This paper describes a reconfigurable 4 × 28 Gb/s transceiver supporting 100 GbE/40 GbE standards. In each lane, the transmitter incorporates a 3-tap FIR with independent output phase adjustment, and the receiver has a half-rate CDR with a dedicated eye-monitor channel. There is a global resonant clock distribution network implemented using programmable distributed on-chip inductors. Implemented in a 40 nm CMOS process, the TX output measures 1.87 pspp DJ and 202 fsrms RJ. The RX jitter tolerance is 0.46 UIpp at 80 MHz with an input sensitivity of 27 mVpp-diff. The transceiver achieves BER on a channel with 20 dB loss at Nyquist, dissipating only 780 mW from a 0.9 V supply for all four lanes at 28 Gb/s operation.

At rates of 100Gb/s and above, CMOS DSP-based transceivers integrated with high-sampling-rate data converters are critical to realize the phase-sensitive modulation schemes based on coherent detection that are essential to metro and long-haul networks [1]. To support dual-polarization QPSK format, quad low-power DACs and ADCs are needed and precise phase alignment has to be maintained between XI, XQ, YI, and YQ channels, in order to transmit and extract the phase information in the coherent system, as shown in Fig. 29.2.1. For long-haul transmission at 100Gb/s, because of the FEC overhead, the baud rate per channel can be as high as 32Gb/s. In addition, the receiver often requires double sampling at 64GS/s for robust clock-data recovery and SNR improvement for stressed channels. Double sampling also enables the DSP to implement more complicated equalization schemes and more flexible spectrum engineering at high frequency on the transmitter side. This paper reports the receiver and transmitter fully integrated in a 100G coherent DSP chip, using 4×64GS/s ADCs and DACs with 8b resolution, fabricated in a standard 20nm CMOS process.

A 39.8-44.6 Gb/s transmitter and receiver chipset designed in 40 nm CMOS is presented. The line-side TX implements a 2-tap FIR filter with delay-based pre-emphasis. The line-side RX uses a quarter-rate CDR architecture. The TX output shows 0.9 pspp ISI and 0.2 psrms RJ at 0.87 W. The RX achieves a jitter tolerance of 0.6 UIpp at 100 MHz and an input sensitivity of 20 mV pp\mathchar"702D diff at 1.05 W. The combined transmitter/receiver equalization enables 44.6 Gb/s data transmission using 231-1 PRBS at BER 10-12 over a channel with >21 dB loss at Nyquist frequency.

An 8.5-11.5-Gbps SONET transceiver with referenceless clock and data recovery (CDR) employing an algorithmic frequency acquisition scheme is presented. Without any training sequence, the frequency acquisition algorithm utilizes a modified digital quadricorrelator frequency detector (M-DQFD) incorporated into an LC-based VCO coarse tuning adjustment. M-DQFD eliminates the dead-zone problem associated with high dispersion and low SNR links. Fabricated in 65-nm CMOS process, the transceiver complies with stringent OC-192 jitter requirements. With a 400- μs acquisition time, the receiver achieves a high-frequency jitter tolerance of 0.58UIpp at 10-mVppd input sensitivity. The transmitter output exhibits a random jitter of 205fsrms. The transceiver occupies 0.97 mm2 and consumes 125 mA at 1.0-V supply voltage.

This paper describes a dual-channel 23 (20 to 27) Gbps chipset designed in a 40-nm CMOS process for 40 Gbps differential quadrature phase-shift keying (DQPSK) optical transmission. The transmitter has a 2-tap FIR filter and generates two channels of full-rate data. Data outputs exhibit 10 ps rise/fall times, 0.2 psrms RJ, 0.8 pspp DJ, and a ±0.5 UI skew adjustment relative to the full-rate and half-rate clock outputs. The receiver has two 20-27-Gbps input channels, with each channel including a peaking filter, decision threshold adjustment, and 1-tap loop-unrolled DFE. It achieves a 7- mVppd input sensitivity and a 0.7-UIpp high-frequency jitter tolerance. The transmitter and receiver dissipate 0.63 and 1.2 W, respectively.

This paper describes an 8.5–11.5 Gb/s transceiver with a dual path receiver and a voltage-mode transmitter. The RX can operate either in ADC mode for complex loss channels such as optical multimode fiber or in DFE mode for copper-based backplane links. The ADC path implements a 2X interleaved 6-bit rectifying flash ADC using a programmable gain amplifier (PGA) with controlled bandwidth and peaking, comparator pipelining, and super-source follower circuit techniques. The LRM optical sensitivity requirements are met with a > 6 dB margin while achieving an ENOB of 4.59 bits at a 5 GHz input frequency. The TX/RX DFE path achieves copper channel loss compensation of 38 dB with BER < 10−12 at 11.5 Gb/s consuming 46mW from a 0.9V supply. The TX/RX ADC path consumes 125 mW at 10.3125 Gb/s. The TX/RX occupies 0.56 mm2 in a 28nm standard CMOS process.

Multilevel modulation formats, such as PAM-4, have been introduced in recent years for next generation wireline communication systems for more efficient use of the available link bandwidth. High-speed ADCs with digital signal processing (DSP) can provide robust performance for such systems to compensate for the severe channel impairment as the data rate continues to increase.

Clock distribution becomes a challenge as clock frequency and chip size keep increasing at the same time. Meanwhile, the distributed effects of the clock channel often show up where clock frequency is high and/or it drives large capacitive loading. In these cases, a standing wave-based structure becomes an attractive technique to deliver a low-jitter clock over a long distance with low power consumption. This paper will explore the properties of a standing wave resonator and its applications in clock distribution. The introduced technique was demonstrated with a design that delivers 5.5GHz quadrature clock to ten lanes of TX/RX and only consumes 12mW. The ten lanes, each running at 11Gbps, showed consistent and excellent jitter performance in measurement, verifying the proposed technique.

In this paper, an 11.3 Gbps CMOS SONET compliant transceiver designed to work in both RZ and NRZ data formats is presented. Using a configurable high-speed transmit path utilizing an AND gate and a duty cycle adjustment circuit, the transmitter can switch output format between RZ and NRZ. The TX driver exhibits 17 ps rise/fall times, 0.25 psrms RJ, and 2 pspp DJ. In RZ mode, TX output duty cycle can be adjusted within 40-60% range. To improve input sensitivity in both RZ and NRZ reception, the receiver incorporates a limiting amplifier with a distributed threshold adjustment circuit. It achieves 5 mVpp-diff RX input sensitivity with 0.54 UI high-frequency jitter tolerance. An adaptation scheme based on nested linear search is implemented to control the distributed threshold adjustment circuit. While demonstrating the integration of RZ/NRZ functionality into a single-chip solution using 65 nm CMOS technology, the transceiver core occupies 1.36 mm2 and consumes 214 mW.

This paper presents the design of an analog-front-end (AFE) integrated into a DSP-based transceiver for both serial 10 Gbps KR-backplane and long-reach-multimode-fiber (LRM) applications. The receiver consists of a programmable gain amplifier (PGA) and a 6-bit 4-way time-interleaved ADC, which is digitally calibrated to compensate for the offset, gain and phase mismatches between the interleaved channels. With a 5 GHz input signal, the ADC achieves overall SNDR of 29 dB, while the measured SNDR of flash sub-ADC is 31.6 dB. The power efficiency FoM of the complete interleaved ADC is 1.4 pJ per conversion step. The PLL uses a calibrated LC-VCO and the TX features a full-rate 3-tap de-emphasis at the output. Inductively tuned buffers connected in tandem are employed to distribute the 10 GHz clock. Random and deterministic jitter measured at the TX output are 0.38 psrms and 2.65 pspp, respectively. Implemented in 65 nm CMOS technology, the AFE occupies an area of 3 mm2 and consumes 500 mW from a 1 V supply. BER of less than 10-15 is measured over legacy backplanes with 26 dB loss at Nyquist and the measured transceiver optical sensitivity is less than -13 dBm for all four LRM stressors, exceeding both the KR and the LRM specifications.

A 7-tap 40 Gb/s FFE using a 65 nm standard CMOS process is described. A number of broadbanding and calibration techniques are used, which allow high-speed operation while consuming 80 mW from a 1 V supply. ESD protection is added to 40 Gb/s IOs and an inexpensive plastic package is used to make the chip closer to a commercial product. The measured tap delay frequency response variation is less than 1 dB up to 20 GHz and tap-to-tap delay variation is less than 0.3 ps. More than 50% vertical and 70% horizontal eye opening from a closed input eye are observed. The use of a CMOS process enables further integration of this core into a DFE equalizer or a CDR/Demux based receiver.

A 10 Gb/s receiver, containing an adaptive equalizer, a clock and data recovery, and a de-multiplexer, is implemented in 0.13-mum CMOS. The chip is intended for long-haul optical fiber links where chromatic and polarization mode dispersions are reach-limiting factors. The equalization is performed by a continuous time filter and a two-tap decision feedback equalizer while automatic threshold and phase adjustments are embedded in the CDR. Use of an analog equalizer with digital adaptation garners total power dissipation of 950 mW. Error-free operation over 200 km of single mode fiber is demonstrated. With 140 km of single mode fiber, optical signal to noise ratio penalty is only 2dB. Differential group delay of 100 ps can also be tolerated