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In this paper, a 7T SRAM cell with differential write and single ended read operations working in the near-threshold region is proposed. The structure is based on modifying a recently proposed 5T cell which uses high and low V TH transistors to improve the read and write stability. To enhance the read static noise margin (RSNM) while keeping the high write margin and low write time, an extra access transistor is used and the threshold voltages of the SRAM transistors are appropriately set. In addition, to maintain the low leakage power of the cell and increase the I on / I off ratio of its access transistors, a high V TH transistor is used in the pull down path of the cell. To assess the efficacy of the proposed cell, its characteristics are compared with those of 5T, 6T, 8T, and 9T SRAM cells. The characteristics are obtained from HSPICE simulations using 20 nm, 16 nm, 14 nm, 10 nm, and 7 nm FinFET technologies assuming a supply voltage of 500 mV. The results reveal high write and read margins, the highest I on / I off ratio, a fast write, and ultra-low leakage power in the hold “0” state for the cell. Therefore, the suggested 7T cell may be considered as one of the better design choices for both high performance and low power applications. Also, the changes of cell parameters when the temperature rises from −40 °C to 100 °C are investigated. Finally, the write margin as well as the read and hold SNMs of the cell in the presence of the process variations are studied at two supply voltages of 400 mV and 500 mV. The study shows that the proposed cell meets the required cell sigma value (6 σ ) under all conditions. [ABSTRACT FROM AUTHOR]

In this work, we investigate the co-dependency of die temperature and bias temperature instability (BTI) and their combined effect on the lifetime of VLSI circuits. The investigation considers the impact of die temperature in increasing the effect of the BTI as well as changes in the die temperature due to the BTI-induced threshold voltage alterations. In addition, the impact of workloads on the degree of the BTI-induced degradation in VLSI circuits is studied. This impact accounts for the direct influence of the signal probability of the internal nodes under the given workload as well as its indirect influence due to power consumption and temperature changes of the circuits. The study is performed by using a simulation framework that captures dynamic changes in the operating temperature and application workload. Simultaneous consideration of the dynamic workload and operating temperature enables one to accurately predict the circuit lifetime. To assess the accuracy of the proposed approach, the estimated delay degradations caused by the Negative BTI (NBTI) for some large circuits from ISCAS'89 and ITC'99 benchmark suites when circuits are simulated under dynamic (both temperature and workload are updated periodically), semi-static (either temperature or workload is updated periodically), and static (no updating is performed) scenarios are compared. Simulation results obtained in a 45 nm CMOS technology, reveal that the predicted timing degradation in the case of the dynamic scenario is significantly different than those of the other scenarios. The differences ranged from − 135% to + 98% for the considered circuits in this work. The large differences demonstrate that for accurate estimation of the circuit lifetime under the BTI effect, the dynamic scenario should be adopted as part of the standard design flows. [ABSTRACT FROM AUTHOR]