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SRAM field-programmable gate arrays (FPGAs) are popular computing platforms for implementing neural networks (NNs) due to their flexibility and low recurring engineering costs. Nevertheless, reliability concerns arise due to their susceptibility to radiation effects, especially considering high-altitude or -scalability applications. In this work, we explore the resilience of quantized, and especially binarized (e.g., use binary values to represent the weights) and nearly binarized, FPGA NNs to neutron-induced errors. Specifically, we study the impact of various NN design parameters, such as the degree of quantization and parallelization, the type of memory for storing the weights, and the diversity of the input images on the NN reliability. To achieve this, we exposed to accelerated atmospheric-like neutron radiation a large set of NN designs built through FINN, a state-of-the-art development framework targeting FPGA NN accelerators, using different quantization, folding, and weight storage schemes. We examine how these parameters affect the tradeoff between area, performance, and reliability, calculating various metrics such as the dynamic cross section (DCS), failures in time (FIT), and mean executions between failures (MEBF). Our findings show that less quantization (i.e., larger bit precision), as well as less folding (i.e., more parallelization), leads to improved reliability (i.e., lower FIT and higher MEBF). In contrast, these two factors push the performance and area of the NNs in opposite directions (i.e., less quantization and folding result in lower latency but more FPGA resources). Moreover, the results reveal that the choice of the memory type (i.e., block RAM (BRAM) or distributed RAM) for storing the NN weights impacts the reliability metrics, with the mixed memory configuration providing the highest reliability.

The AMD UltraScale+ XCZU9EG, a multiprocessor system-on-chip (MPSoC) with integrated programmable logic (PL), is vulnerable to the effects of atmospheric radiation due to its large SRAM count. This article explores the effectiveness of the MPSoC's embedded soft-error mitigation mechanisms through accelerated atmospheric-like neutron radiation testing and dependability analysis. We test the device on a broad range of workloads, such as multithreaded software for pose estimation and weather prediction and a software/hardware codesign image classification application running on the AMD deep-learning processing unit (DPU). We found that for a one-node MPSoC system in New York City at 40 k feet (e.g., avionics), software applications demonstrate a mean time to failure (MTTF) of over 121 months, evidencing effective upset recovery. However, specific workloads, such as the DPU, displayed an MTTF of 4 months, which is attributed to the high failure rate of its PL accelerator. Yet, we show the DPU's MTTF can be extended to 87 months with no extra overhead by ignoring the failure rate of tolerable errors since these do not affect the DPU results.