Search

Consumer-electronics systems are becoming increasingly complex as the number of integrated applications is growing. Some of these applications have real-time requirements, while other non-real-time applications only require good average performance. For cost-efficient design, contemporary platforms feature an increasing number of cores that share resources, such as memories and interconnects. However, resource sharing causes contention that must be resolved by a resource arbiter, such as Time-Division Multiplexing. A key challenge is to configure this arbiter to satisfy the bandwidth and latency requirements of the real-time applications, while maximizing the slack capacity to improve performance of their non-real-time counterparts. As this configuration problem is NP-hard, a sophisticated automated configuration method is required to avoid negatively impacting design time. The main contributions of this article are: (1) an optimal approach that takes an existing integer linear programming (ILP) model addressing the problem and wraps it in a branch-and-price framework to improve scalability. (2) A faster heuristic algorithm that typically provides near-optimal solutions. (3) An experimental evaluation that quantitatively compares the branch-and-price approach to the previously formulated ILP model and the proposed heuristic. (4) A case study of an HD video and graphics processing system that demonstrates the practical applicability of the approach.

The complexity of embedded application design is increasing with growing user demands. In particular, automotive embedded systems are highly complex in nature, and their functionality is realized by a set of periodic tasks. These tasks may have hard real-time requirements and communicate over an interconnect. The problem is to efficiently co-schedule task execution on cores and message transmission on the interconnect so that timing constraints are satisfied. Contemporary works typically deal with zero-jitter scheduling, which results in lower resource utilization, but has lower memory requirements. This article focuses on jitter-constrained scheduling that puts constraints on the tasks jitter, increasing schedulability over zero- jitter scheduling. The contributions of this article are: 1) Integer Linear Programming and Satisfiability Modulo Theory model exploiting problem-specific information to reduce the formulations complexity to schedule small applications. 2) A heuristic approach, employing three levels of scheduling scaling to real-world use-cases with 10000 tasks and messages. 3) An experimental evaluation of the proposed approaches on a case-study and on synthetic data sets showing the efficiency of both zero-jitter and jitter- constrained scheduling. It shows that up to 28% higher resource utilization can be achieved by having up to 10 times longer computation time with relaxed jitter requirements., Comment: IEEE Transactions on Computers (2017)

The design of mixed-criticality systems often involvespainful tradeoffs between safety guarantees and performance.However, the use of more detailed architectural modelsin the design and analysis of scheduling arrangements for mixedcriticalitysystems can provide greater confidence in the analysis,but also opportunities for better performance. Motivated by thisview, we propose an extension of Vestal 19s model for mixedcriticalitymulticore systems that (i) accounts for the per-taskpartitioning of the last-level cache and (ii) supports the dynamicreassignment, for better schedulability, of cache portions initiallyreserved for lower-criticality tasks to the higher-criticalitytasks, when the system switches to high-criticality mode. Tothis model, we apply partitioned EDF scheduling with Ekbergand Yi 19s deadline-scaling technique. Our schedulability analysisand scalefactor calculation is cognisant of the cache resourcesassigned to each task, by using WCET estimates that take intoaccount these resources. It is hence able to leverage the dynamicreconfiguration of the cache partitioning, at mode change, forbetter performance, in terms of provable schedulability. We alsopropose heuristics for partitioning the cache in low- and highcriticalitymode, that promote schedulability. Our experimentswith synthetic task sets, indicate tangible improvements inschedulability compared to a baseline cache-aware arrangementwhere there is no redistribution of cache resources from low- tohigh-criticality tasks in the event of a mode change., Comment: ECRTS 2017, 26 pages