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Although metal/ferroelectric/semiconductor tunnel junctions have been attracting widespread interest as next-generation memory devices, only limited effort has been devoted so far to quantitatively address their current–voltage characteristics and their achievable memory window. In this article, we show experimental data on template Pt/BaTiO3/Nb:SrTiO3 tunnel junctions confirming, first of all, that large memory windows can be achieved in these devices when the switching of the electric polarization in the ferroelectric layer moves the substrate between an accumulation and a depletion condition. Besides, by measuring the current–voltage curve of the devices quickly after the set/reset pulses used for polarization switching, the importance of considering the detrimental effects of the large depolarization fields in the ferroelectric layer when assessing the device memory window is demonstrated. The experimental data are, then, reproduced by a model for electron transport through the junction accounting for both drift/diffusion and distributed tunneling in the semiconductor. The model allows to catch a comprehensive physical picture of device operation and represents a powerful tool for the design and optimization of ferroelectric tunnel junctions with semiconductor electrodes.

In this work, we investigate the implementation of a neuromorphic digit classifier based on NOR Flash memory arrays as artificial synaptic arrays and exploiting a pulse-width modulation (PWM) scheme. Its performance is compared in presence of various noise sources against what achieved when a classical pulse-amplitude modulation (PAM) scheme is employed. First, by modeling the cell threshold voltage (VT) placement affected by program noise during a program-and-verify scheme based on incremental step pulse programming (ISPP), we show that the classifier truthfulness degradation due to the limited program accuracy achieved in the PWM case is considerably lower than that obtained with the PAM approach. Then, a similar analysis is carried out to investigate the classifier behavior after program in presence of cell VT instabilities due to random telegraph noise (RTN) and to temperature variations, leading again to results in favor of the PWM approach. In light of these results, the present work suggests a viable solution to overcome some of the more serious reliability issues of NOR Flash-based artificial neural networks, paving the way to the implementation of highly-reliable, noise-resilient neuromorphic systems.

This article and its part II demonstrate the possibility to operate a mainstream NOR Flash memory array as an artificial synaptic array learning without external supervision according to the spike-timing-dependent plasticity (STDP) rule. As a first mandatory step to this aim, suitable array working conditions allowing not only selective cell programming but also selective cell erase are here identified, overcoming the block erase operation typical of any Flash memory technology. The proposed array working conditions exploit channel hot-electron injection and hot-hole injection at the drain side to achieve selective, bidirectional, and virtually analog tuning of cell threshold voltage, with no need for changes in the design of a common-ground double-polysilicon NOR array. In part II, the new working scheme will be shown to allow for a straightforward implementation of STDP and unsupervised learning in the array.

This work addresses the methodology and implementation of a neuromorphic SNN system to compute the temporal information among neural spikes using ReRAM synapses capable of spike-timing dependent plasticity (STDP)., Resistive switching random-access memory (ReRAM) is a two-terminal device based on ion migration to induce resistance switching between a high resistance state (HRS) and a low resistance state (LRS). ReRAM is considered one of the most promising technologies for artificial synapses in brain-inspired neuromorphic computing systems. However, there is still a lack of general understanding about how to develop such a gestalt system to imitate and compete with the brain’s functionality and efficiency. Spiking neural networks (SNNs) are well suited to describe the complex spatiotemporal processing inside the brain, where the energy efficiency of computation mostly relies on the spike carrying information about both space (which neuron fires) and time (when a neuron fires). This work addresses the methodology and implementation of a neuromorphic SNN system to compute the temporal information among neural spikes using ReRAM synapses capable of spike-timing dependent plasticity (STDP). The learning and recognition of spatiotemporal spike sequences are experimentally demonstrated. Our simulation study shows that it is possible to construct a multi-layer spatiotemporal computing network. Spatiotemporal computing also enables learning and detection of the trace of moving objects and mimicking of the hierarchy structure of the biological visual cortex adopting temporal-coding for fast recognition.

In this paper, we compare quantitatively the results obtained from the numerical simulation of current transport in polysilicon-channel MOSFETs under different modeling assumptions typically adopted to reproduce the basic physics of the devices, including the effective medium approximation and the description of polysilicon as the haphazard ensemble of monocrystalline silicon grains separated by highly defective grain boundaries. In the latter case, both pure drift-diffusion transport and a mix of intra-grain drift-diffusion and inter-grain thermionic emission are considered. Interest is focused on cylindrical nanowire and macaroni gate-all-around structures, due to their relevance in the field of 3-Dimensional NAND Flash memories, focusing not only on the average behavior but also on the variability in the electrical characteristics of the devices.

This paper covers the recent evolution of high-density solid-state storage, which is the most prominent storage solution of the 21st century. The attention is focused on the two integrated technologies that more than any other are revolutionizing the storage landscape: the NAND Flash technology and the Phase-Change Memory (PCM) technology. The success of the NAND Flash technology has been the outcome of its strenuous attempt not only to maximize the bit storage density achievable with a cost-effective process over the surface of a silicon die, but also to increase that density at a regular pace thanks to favorable evolutionary approaches. In this way, NAND Flash memories have become the elective storage media for a wide variety of electronic applications, overwhelming hard-disk drives. The PCM technology represents, instead, a notable exploitation of a new memory concept to provide a novel trade-off among cost, performance and reliability. In particular, the PCM attempt to address performance more than cost needs is driving a shift in the traditional storage hierarchy, with storage-class memory finally becoming a reality.

We show that a Meyer-Neldel (MN) regime, usually reported for disordered materials, is found in state-of-the-art monocrystalline Si MOSFETs. This unexpected result is explained via device simulation in terms of the self-consistency between the mobile charge and the device electrostatics. The dependence on device parameters is then discussed, showing that neglecting this effect can lead to interpretation errors for data evaluated at low activation energies.

In this article and the related Part II, we investigate variability effects on the threshold voltage of nanowire and Macaroni MOSFETs, focusing on random dopant fluctuations (RDFs) and random telegraph noise, to assess their dependences on device radius, channel length, and doping. In Part I, we address threshold voltage fluctuations induced by RDF and show that different trends emerge with respect to planar devices, being dependent on whether the conduction is bulk- or surface-dominated. Macaroni devices with thin silicon regions can improve RDF, while moving from inversion- to accumulation-mode devices results in a worsening of this parameter.

We review the impact of random telegraph noise (RTN) on the operation of NOR and NAND Flash memories. We begin with a comprehensive set of experimental data for the RTN distribution within Flash arrays, including cycling and temperature dependences, moving then to the physical interpretation of the phenomenon and model description. RTN effect on the programmed threshold voltage is then addressed. Finally, we review the impact of RTN in 3D NAND Flash and its relation to their polycrystalline channel, from an experimental and theoretical standpoint.

This paper presents characterization and modeling results exploring the temperature dependence of the electrical characteristics of 3-D NAND Flash strings. Experimental data over a wide temperature range are used to calibrate a Technology Computer-Aided Design model for current transport through the polysilicon channel of the strings, which is then used to investigate the role of grain boundaries on string conduction. Results reveal that the variability in the grain configuration in the strings introduces a nonnegligible statistical spread in the temperature dependence of the threshold voltage ( ${V}_{T}$ ) of the memory cells, which acts as a broadening contribution to the array ${V}_{T}$ distribution when temperature is changed. The experimental and modeling activities will be extended in Part II of this paper to explore the temperature dependence of the ${V}_{T}$ instability caused by random telegraph noise.

This paper investigates the temperature dependence of random telegraph noise (RTN) in 3-D NAND Flash technologies. Experimental results on memory arrays reveal an increase of RTN when temperature is reduced, which is mainly attributed to the growth of the amplitude of the fluctuations arising from RTN traps. A direct proof of this growth is provided by directly monitoring some RTN waveforms arising from single traps in cells out of either memory arrays or test elements. In order to explain this evidence, the TCAD model for polysilicon NAND strings presented in Part I of this paper is adopted and extended to address the amplitude of the threshold-voltage shift coming from the trapping of a single electron at different positions in cell channel. Numerical results successfully reproduce the experimental trends with temperature and allow to explain them in terms of stronger nonuniformities in polysilicon inversion when temperature decreases. In particular, the reduction of temperature makes the string currentmore controlledby the polysilicon grain boundaries, increasing, in turn, the amplitude of the RTN fluctuations arising from traps placed on or close to them.

This paper presents a detailed analysis of the time dynamics of the gate-induced drain leakage (GIDL)-assisted increase of the string potential in vertical-channel 3-D NAND Flash arrays. The string potential and the GIDL current waveforms are first studied with close attention by means of technology computer-aided design simulations, highlighting the major phases of their time evolution. A compact model able to reproduce the string behavior is then presented and successfully tested for a variety of electrical waveforms applied to the string contacts, for increasing number of cells in the string and for different string geometrical parameters. The compact model represents a valuable tool to design and optimize the GIDL conditions for the best erase performance.

In this work, we investigate the impact of program accuracy and of the time instabilities in cell threshold-voltage (V T ) arising from random telegraph noise (RTN) on the performance of a neuromorphic digit classifier exploiting NOR Flash arrays as artificial synaptic arrays. First, by modeling cell V T placement resulting from a program-and-verify algorithm based on incremental step pulse programming (ISPP) in the presence of program noise, the classifier truthfulness is investigated as a function of the discretization step of the verify level and of the cell control-gate–to–floating-gate capacitance. Then, the degradation of the classifier accuracy due to RTN fluctuations displacing cell V T from its programmed value is addressed as a function of the most relevant RTN statistical parameter, i.e., the average value of the single-trap fluctuation amplitude. Results highlight some quantitative criteria to determine how scaled NOR Flash cells and arrays can be when targeting neuromorphic applications.

In this work, we compare different modeling approaches typically adopted to address current transport in polysilicon-channel MOSFETs. The analysis is focused on cylindrical gate-all-around devices with deca-nanometer dimension, due to the strong relevance recently gained by such devices in the field of 3-D NAND Flash memories. Pure drift-diffusion simulations under the effective medium approximation are compared to simulations accounting for polysilicon grains and grain boundaries, either keeping pure drift-diffusion transport or mixing intra-grain drift-diffusion with inter-grain thermionic emission. Some nonnegligible differences among the predictions of the three modeling approaches are highlighted and explained as a function of the device working regime, temperature and average size of the polysilicon grains. Results represent an important step towards a better understanding and a better extraction of the parameters of polysilicon-channel devices.

This paper reviews what changed in the reliability of NAND Flash memory arrays after the paradigm shift in technology evolution determined by the transition from 2-D to 3-D integration schemes. Starting from a quick glance at the fundamentals of raw array reliability, the reasons for its worsening with the evolution of 2-D technologies will be discussed, focusing on the physical phenomena which contributed more to that outcome. By exploring the dependence of the magnitude of these phenomena on cell and array parameters, the abrupt improvements achieved from the 3-D transition in terms of raw array reliability will then be explained, highlighting also that these improvements were turned into new opportunities for the technology. Finally, the physical issues specific to 3-D arrays will be addressed, providing a glimpse of the challenges that the NAND Flash technology will have to face from the standpoint of array reliability in the near future.

This paper presents a physics-based compact model able to describe the time dynamics of the erase operation in three-dimensional NAND Flash strings exploiting gate-induced drain leakage at the selector to increase the string potential. The model accurately reproduces all the main phases of the erase operation and allows to calculate the threshold voltage transient arising from hole injection into and electron emission from the gate stack of the memory cells, accounting for the correct cylindrical geometry of the string. Thanks to its simple structure, the model is suitable for parametric analyses aiming at optimizing the string structure and the operating waveforms from the standpoint of the erase performance.

In this article, we show that, by exploiting the program and erase conditions identified in Part I of this article, operating a mainstream NOR Flash memory array as an artificial synaptic array learning in an unsupervised manner according to the spike-timing-dependent plasticity (STDP) rule can be easily achieved. To this aim, first, a word-line and a bitline voltage scheme allowing cells to change their memory state and, in turn, their synaptic weight to mimic the STDP learning rule is presented. Then, a simple spiking neural network making use of the NOR Flash array as a synaptic array is discussed along with its basic operating waveforms. Finally, the proof of concept for unsupervised learning in the array of a signal pattern provided at the network inputs is given.

This paper exploits the possibility of monitoring the floating-gate (FG) charge of state-of-the-art NAND Flash arrays with a single-electron resolution to investigate in detail the program operation and some previously inaccessible technological parameters. In particular, the analysis leads to the assessment of the statistical distribution of the FG to control-gate capacitance and of the leakage current from the FG through the intergate dielectric during the programming pulses. Results highlight that resolving the FG charge at the single-electron level opens new prospects for the investigation of the operation and the parameters of NAND Flash arrays.

In this work, we present the first implementation of spike-timing-dependent plasticity (STDP) and unsupervised learning in a mainstream NOR Flash memory array based on floating-gate cells. A simple yet effective word-line and bit-line pulse scheme is proposed to make a common-ground double-polysilicon NOR array in 40 nm embedded technology work as an artificial synaptic array in a spiking neural network learning according to the STDP rule, with no change required either to the array or to the cell design. With this scheme, long-term potentiation and long-term depression of the synaptic weights are achieved, respectively, by hot-hole injection and channel hot-electron injection at the drain side of the cells. Unsupervised learning is experimentally demonstrated in the array, paving the way for the development of large-scale and high-density neuromorphic systems based on mainstream nonvolatile memory technologies.

We present a systematic investigation of random dopant fluctuations and random telegraph noise instabilities in Nanowire and Macaroni MOSFETs via 3D atomistic Monte Carlo simulations. We discuss their dependence on geometry and doping and show that different trends appear with respect to planar devices. Some unexpected results are explained in terms of 3D percolation and electrostatic intearitv of the structures.

Brain-inspired computation can revolutionize information technology by introducing machines capable of recognizing patterns (images, speech, video) and interacting with the external world in a cognitive, humanlike way. Achieving this goal requires first to gain a detailed understanding of the brain operation, and second to identify a scalable microelectronic technology capable of reproducing some of the inherent functions of the human brain, such as the high synaptic connectivity (~10

Hardware processors for neuromorphic computing are gaining significant interest as they offer the possibility of real in-memory computing, thus by-passing the limitations of speed and energy consumption of the von Neumann architecture. One of the major limitations of current neuromorphic technology is the lack of bio-realistic and scalable devices to improve the current design of artificial synapses and neurons. To overcome these limitations, the emerging technology of resistive switching memory has attracted wide interest as a nano-scaled synaptic element. This paper describes the implementation of a perceptron-like neuromorphic hardware capable of spike-timing dependent plasticity (STDP), and its operation under stochastic learning conditions. The learning algorithm of a single or multiple patterns, consisting of either static or dynamic visual input data, is described. The impact of noise is studied with respect to learning efficiency (false fire, true fire) and learning time. Finally, the impact of stochastic learning rule, such as the inversion of the time dependence of potentiation and depression in STDP, is considered. Overall, the work provides a proof of concept for unsupervised learning by STDP in memristive networks, providing insight into the dynamics of stochastic learning and supporting the understanding and design of neuromorphic networks with emerging memory devices.

Resistive switching devices were used as technological synapses to learn about the spatial- and temporal-correlated neuron spikes., The human brain is a complex integrated spatiotemporal system, where space (which neuron fires) and time (when a neuron fires) both carry information to be processed by cognitive functions. To parallel the energy efficiency and computing functionality of the brain, methodologies operating over both the space and time domains are thus essential. Implementing spatiotemporal functions within nanoscale devices capable of synaptic plasticity would contribute a significant step toward constructing a large-scale neuromorphic system that emulates the computing and energy performances of the human brain. We present a neuromorphic approach to brain-like spatiotemporal computing using resistive switching synapses. To process the spatiotemporal spike pattern, time-coded spikes are reshaped into exponentially decaying signals that are fed to a McCulloch-Pitts neuron. Recognition of spike sequences is demonstrated after supervised training of a multiple-neuron network with resistive switching synapses. Finally, we show that, due to the sensitivity to precise spike timing, the spatiotemporal neural network is able to mimic the sound azimuth detection of the human brain.

This paper presents a comprehensive simulation analysis of the dynamic operation of T-RAM cells. The analysis addresses the evolution of cell electrostatics and of carrier concentrations and flows in the device when the gate voltage undergoes a fast low-to-high switch, as required by both read and write operations. The results clarify, first of all, the basic physics making holes in the p-base the physical element allowing information storage in the device. From this starting point, the working principles exploited for DRAM operation of the memory cell are then explained.