257 results on '"Alpert, Charles J."'
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2. ISPD 2005/2006 Placement Benchmarks
3. A fully polynomial-time approximation scheme for timing-constrained minimum cost layer assignment
4. RUMBLE: an incremental timing-driven physical-synthesis optimization algorithm
5. Diffusion-based placement migration with application on legalization
6. Fast algorithms for slew-constrained minimum cost buffering
7. Path-based buffer insertion
8. Accurate estimation of global buffer delay within a floorplan
9. A fast hierarchical quadratic placement algorithm
10. Closed-form delay and slew metrics made easy
11. Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees
12. Porosity-aware buffered Steiner tree construction
13. A delay metric for RC circuits based on the Weibull distribution
14. Optimal path routing in single- and multiple-clock domain systems
15. Effective free space management for cut-based placement via analytical constraint generation
16. A practical methodology for early buffer and wire resource allocation
17. Buffer insertion with adaptive blockage avoidance
18. Minimum buffered routing with bounded capacitive load for slew rate and reliability control
19. Buffered Steiner trees for difficult instances
20. Introduction to Physical Design
21. Placement-Driven Synthesis Design Closure Tool
22. Buffer insertion for noise and delay optimization
23. Splitting an Ordering into a Partition to Minimize Diameter
24. Multilevel circuit partitioning
25. Faster minimization of linear wirelength for global placement
26. Multiway partitioning via geometric embeddings, orderings, and dynamic programming
27. Probability-driven routing in a datapath environment
28. MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes
29. Prim-Dijkstra Revisited
30. Spectral partitioning with multiple eigenvectors
31. MrDP
32. Editorial
33. Shedding Physical Synthesis Area Bloat
34. Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography
35. Editorial
36. Stitch aware detailed placement for multiple e-beam lithography.
37. PACMAN
38. Techniques for scalable and effective routability evaluation
39. Clock power minimization using structured latch templates and decision tree induction
40. Routing congestion estimation with real design constraints
41. Structure-Aware Placement Techniques for Designs With Datapaths
42. CATALYST: Planning Layer Directives for Effective Design Closure
43. Clock power minimization using structured latch templates and decision tree induction.
44. GLARE
45. Guiding a physical design closure system to produce easier-to-route designs with more predictable timing
46. MAPLE
47. Quantifying academic placer performance on custom designs
48. The ISPD-2011 routability-driven placement contest and benchmark suite
49. Design-hierarchy aware mixed-size placement for routability optimization
50. Detecting tangled logic structures in VLSI netlists
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