86 results on '"Amaricai, Alexandru"'
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2. Low-Cost Hardware Infrastructure for Runtime Thread Level Energy Accounting
3. Using Cycle-Approximate Simulation for Bus Based Multi-Processor System-On Chip Analysis
4. Design Trade‐Offs for FPGA Implementation of LDPC Decoders
5. Memory trade-offs in layered self-corrected min-sum LDPC decoders
6. Low-Cost Hardware Infrastructure for Runtime Thread Level Energy Accounting
7. Generalized Very High Throughput Unrolled LDPC Layered Decoder
8. Fault Tolerant Digital Data-Path Design via Control Feedback Loops
9. Using Cycle-Approximate Simulation for Bus Based Multi-Processor System-On Chip Analysis
10. Layered LDPC decoder in-order message access scheduling: a case study
11. Configurable Hardware Accelerator Architecture for a Takagi-Sugeno Fuzzy Controller
12. A Log-Likelihood Ratio based Generalized Belief Propagation
13. Layered LDPC Decoders With Efficient Memory Access Scheduling and Mapping and Built-In Support for Pipeline Hazards Mitigation
14. Design Trade‐Offs for FPGA Implementation of LDPC Decoders
15. Memory-Centric Flooded LDPC Decoder Architecture Using Non-surjective Finite Alphabet Iterative Decoding
16. Unrolled layered architectures for non-surjective finite alphabet iterative decoders
17. Ultra High Throughput Unrolled Layered Architecture for QC-LDPC Decoders
18. Design Trade-offs in Configurable FPGA Architectures for K-Means Clustering
19. On the Redundant Representation of Partial Remainders in Radix-4 SRT Dividers
20. Reliability analysis of memory centric LDPC decoders under probabilistic storage failures
21. Cost effective FPGA implementation for hard decision LDPC decoders
22. Variable throughput LDPC decoders using SIMD-based adaptive quantization
23. Configurable FPGA architecture for hardware-software merge sorting
24. FPGA architecture of multi-codeword LDPC decoder with efficient BRAM utilization
25. Memory trade-offs in layered self-corrected min-sum LDPC decoders
26. Multi-level probabilistic timing error reliability analysis using a circuit dependent fault map generation
27. Timing error analysis of flooded LDPC decoders
28. Memory efficient FPGA implementation for flooded LDPC decoder
29. Analysis and implementation of on-the-fly stopping criteria for layered QC LDPC decoders
30. Generation of floating point 2D translation operators for FPGA
31. Direct FPGA-based power profiling for a RISC processor
32. Sub-threshold CMOS circuits reliability assessment using simulated fault injection based on simulator commands
33. Performance Enhancement of Serial Based FPGA Probabilistic Fault Emulation Techniques
34. Cost-efficient FPGA layered LDPC decoder with serial AP-LLR processing
35. An FPGA sliding window-based architecture harris corner detector
36. Probabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS Circuits
37. Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits
38. Low‐precision DSP‐based floating‐point multiply‐add fused for Field Programmable Gate Arrays
39. Probabilistic saboteur-based simulated fault injection techniques for low supply voltage interconnects
40. SRT radix-2 dividers with (5,4) redundant representation of partial remainder
41. FPGA implementation of very high radix square root with prescaling
42. A cycle-count-accurate simulation platform with enhanced design exploration capability
43. Models and implementations of hardware interface modules in a multi-processor system-on-chip simulator
44. Design Issues and Implementations for Floating-Point Divide–Add Fused
45. Improving the Performance of the Divide-Add Fused Operation Using Variable Latency Quotient Generation
46. Reliability Analysis of Qubit Data Movement for Distributed Quantum Computation
47. Design of floating point units for interval arithmetic
48. Error-Model Driven Analysis of Quantum Circuits Reliability
49. Floating point multiplication rounding schemes for interval arithmetic
50. A Dual-Threaded Architecture for Interval Arithmetic Coprocessor with Shared Floating Point Units
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