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6. Investigation of Random Telegraph Noise Under Different Programmed Cell V t Levels in Charge Trap Based 3D NAND Flash.

8. Experimental and simulation study of 1D silicon nanowire transistors using heavily doped channels

11. Interplay between quantum mechanical effects and a discrete trap position in ultrascaled FinFETs

12. Statistical simulations of 6T-SRAM cell ageing using a reliability aware simulation flow

22. Investigation of the ISPP dynamics and of the programming efficiency of charge-trap memories

23. Reliability constraints for TANOS memories due to alumina trapping and leakage

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