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Currently, DNA strand displacement is often used to build neural networks or solve logical problems. While there are few studies on the use of DNA strand displacement to solve the higher order equations. In this paper, the catalysis, degradation, annihilation and adjusted reaction modules are built through DNA strand displacement. The chemical reaction networks of the corresponding higher order equations and simultaneous equations are established through these modules, and these chemical reaction networks can be used to build analog circuits to solve binary primary simultaneous equations and binary quadratic simultaneous equations. Finally, through Visual DSD software verification, this design can realize the solution of binary primary simultaneous equations and binary quadratic simultaneous equations, which provides a reference for DNA computation in the future.

Analog and mixed-signal (AMS) blocks are often a crucial and time-consuming part of System-on-Chip (SoC) design, primarily due to manual circuit and layout iterations. Existing automated solutions for selecting circuit parameters for a given target specification are often not efficient, accurate, or reliable. In order for an automated sizing tool to be practical, we posit that it must: 1) return valid results for a large range of target specifications, 2) understand where and why it is unable to meet certain specifications, 3) consider true layout parasitic simulations for complete end-to-end design, and 4) be automated, allowing most of the design effort to fall on the tool. In this paper, we address these critical points by establishing an automated reinforcement learning framework, AutoCkt, by 1) successfully deploying it on a complex two-stage transimpedance amplifier and two-stage folded-cascode with biasing in 16nm FinFet technology, 2) implementing a new combined distribution deployment algorithm to improve efficiency, 3) analyzing in-depth the efficacy of the trained agent and 4) demonstrating the functionality of this tool when considering a topology that is highly sensitive to layout parasitics. Our algorithm not only successfully reaches unique, valid, and practical performances, but also does so in state-of-the-art run time, up to 38X more efficient than prior work. In addition, our tool averages just four parasitic simulations obtained by using the Berkeley Analog Generator, to achieve a target specification post-layout for the folded-cascode. AutoCkt successfully generates LVS-passed designs with validation in process corner variation results.

A spectrum of emerging applications including edge artificial intelligence advocate the precompute-and-search scheme with embedded small-size content addressable memory (CAM) for its hardware efficiency instead of repetitive arithmetic operations. However, integration of the CAM macros that are conventionally implemented with full custom analog circuits renders design-space exploration and optimization to be difficult at system level. As an alternative, a complete design flow for compiling ternary CAM on chip using foundry-supplied digital standard cells is introduced in this paper. Based on novel CAM architecture and logic design, we leverage guided placement and routing with mainstream EDA tools for exploiting the inherent structure regularity of CAM-cell arrays in layout. An analytical model is also presented which allows us for a systematic investigation on the energy reduction by adapting our design to various pre-search structures. Validated on a post-layout 32W64 ternary CAM in 28nm, our parallel-matching scheme performs at 2.6GHz with 0.42fJ/bit/search, and the (8-bit) pre-search scheme achieves 0.19fJ/bit/search at 1.1GHz, both under the 0.9V supply voltage. In addition to flexibility for tradeoffs between the search throughput and energy, our all-digital CAM design enables voltage scaling aggressively down to 0.45V with a minimum energy consumption of 0.06fJ/bit/search at 50MHz.

Building a post-layout simulation performance model is essential in closing the loop of analog circuits, but it is a challenging task because of the high-dimensional space and expensive simulation cost. To facilitate efficient modeling, this paper proposes a Global Mapping Model Fusion (GMMF) technique. The key idea of GMMF is to reuse the schematic-level model trained by the Artificial Neural Network (ANN) algorithm, and combine it with few mapping coefficients to build the post-simulation model. Furthermore, as an efficient global optimization algorithm, differential evolution is applied to determine the optimal mapping coefficients with few samples. In GMMF, only a small number of mapping coefficients are unknown, so the number of post-layout samples needed is significantly reduced. To enhance practical utility of the proposed GMMF technique, two specific mapping relations, i.e., linear or weakly no-linear and nonlinear, are carefully considered in this paper. We conduct experiments on two topologies of two-stage operational amplifier and comparator in different commercial processes. All the simulation data for modeling are obtained from a parametric design framework. A more than 5× runtime speedup is achieved over ANN without surrendering any accuracy.

Most analog circuits need a current reference generator to provide a stable biasing point for the transistors. Given the limited voltage headroom in advanced node technologies, there would be notable restrictions on the tolerance of the reference current deviation. Use of off-chip reference generators adds to the size of the system while the on-chip reference current generators are still partially dependent on the on-chip resistor values which is prone to technology variations. We propose an on-chip reference generator with a fully off-chip resistor which has less sensitivity to process variations. Monte-Carlo simulation results shows that the proposed has 31% more precision compared to the conventional on-chip reference generator. Measurement results in 0.18 μm CMOS shows that the chip produces a stable reference current that is defined based on an off-chip resistor. The proposed structure consumes the same current as conventional and does not add to the power consumption.

A novel driving circuit for a current doubler synchronous rectifier to inductive power transfer (IPT) applications is proposed in this paper using only auxiliary windings in the existent rectifier output filter inductors to drive the active switches. The proposed synchronous rectifier (SR) overcomes the limitations of the traditional driving schemes because it does not require any processing, analog circuits, gate drivers circuits or current measurement, normally used in the conventional SR applied to IPT systems. The proposed configuration presents a simple and robust operation considering usual parametric variation in IPT systems, such as coupling factor, misalignment, load variation and component tolerances. Moreover, the same size and weight of the conventional diode rectifier board is maintained due to the simplicity of the self-driven circuit. The proposed configuration allows increasing the global efficiency by reducing the conduction losses of the output rectifier and previous stages. A resonant circuit design procedure using an iterative process to find the maximum efficiency point considering the self-driven SR is proposed to maximize the global system efficiency. A 100 W resonant series-parallel IPT prototype is developed to validate the performance of the proposed self-driven SR circuit presenting a maximum global efficiency equal to 94.8%.

Traditional power factor correction (PFC) converters usually employ a large electrolytic capacitor to ensure a stiff output voltage. However, the electrolytic capacitor is not expected in terms of the reliability and the size of the system. This article proposes a peak and valley current control for Cuk PFC converter to remove the bulky electrolytic capacitor. The proposed control is realized by a combination of analog and digital circuits. The analog circuits are used to accomplish the real-time comparison between the actual currents and their reference values. And the digital circuits are employed to deal with simple logical judgement. Different from the existing full digital control technique, which needs a high-quality digital signal processor (DSP) to process complex arithmetic operation, the proposed control concept even can only require a low performance microcontroller unit. Besides, the control delay is avoided. This article first analyzes the operation stages of the Cuk PFC converter. Then, design considerations of main circuit and control circuit are introduced. Finally, the experimental results from 200W Cuk PFC converter are presented to verify the effectiveness of the proposed control.

Analog circuit design can be formulated as a non-linear constrained optimisation problem that can be solved using any suitable optimisation algorithms. Different optimisation techniques have been reported to reduce the design time of analog circuits. A hybrid particle swarm optimisation algorithm with linearly decreasing inertia weight for the optimisation of analog circuit design is proposed in this study. The proposed method is used to design a two-stage operational amplifier circuit with Miller compensation. The results show that the proposed optimisation method can substantially reduce the design time needed for analog circuits.

In this article, a mixed-signal, 32-kHz reference-based 2.4-GHz fractional-N over-sampling phase-locked loop (OSPLL) is proposed. Different from the conventional 1x sampling PLL, which only uses zero-crossing timing information of the reference signal, the proposed OSPLL fully utilizes both the voltage and timing domain information of the reference signal and realizes oversampling ratio (OSR) times phase detection (PD) in one reference cycle. The proposed OSPLL employs the digital-to-analog converter (DAC) to construct the reference-like feedback signal in the voltage domain and utilizes the digital-to-time converter (DTC) to improve PD resolution in the time domain. The adaptive lookup table (LuT)-based calibration is proposed to generate the correct information for DAC and DTC control. A clocked passive comparator works as a bang-bang phase detector (BBPD) for the PLL control and LuTs' construction. The co-design of low-noise analog circuits and digital calibrations enables good jitter and spur performance. The proposed OSPLL is fabricated in 65-nm CMOS technology, with the core area of 0.58 mm², and the power consumption is 4.97 mW with a 1-V power supply. It achieves 5.79-ps root-mean-square (rms) jitter in fractional-N modes with the loop-bandwidth (BW $_{loop}$ ) of 200 kHz, corresponding to the figures of merit (FoMs) of -217.8 dB. The measured fractional spur is less than -36 dBc, and the reference spur is -78 dBc, respectively.

In this paper, the sine function memristor and the cosine function memristor are connected in series, and the constructed series memristor is numerically analyzed through its volt-ampere characteristics, and then the new memristor was introduced into the Rossler system to construct a hyperchaotic system with dual memory elements. The coexistence attractor and fractal phenomena in the system are analyzed, and the fractal dimension of the system is calculated on the basis of fractal theory. In addition, analog circuits corresponding to the system are designed and simulated based on circuit theory. DSP is used for digital circuit experiments to explore the application of this system in practice.

Oscillation-based test algorithm has been proposed and verified experimentally as an alternative to the specification--based test of analog circuits. Active filters are transformed to oscillators u...

Several automatic analog integrated circuit (IC) sizing tools have been proposed and successfully applied to multi-objective circuit design problems over the last two decades. However, rendering those tools yield-aware has not been fully addressed yet since inclusion of variability analysis to the optimization loop is still a bottleneck due to the tremendous trade-off between accuracy and efficiency of the synthesis process. Conventional Monte Carlo (MC) based approaches are quite accurate, but, they are highly inefficient due to cumbersome simulation effort. Even though employing enhanced sampling techniques, e.g., Latin Hypercube Sampling (LHS), exhibits slightly better efficiency, the accuracy of such approaches is still less than Monte Carlo. To palliate this problem, in this paper, we propose a novel Deep Neural Network (DNN) aided MC simulation framework for yield-aware analog circuit sizing. In the developed tool, the DNN is leveraged to develop circuit models during the optimization, which are then used to estimate the effects of variations in device dimensions without any simulation effort while some additional simulations are concurrently carried out for V t h variations. Finally, once DNN based circuit models are obtained, the simulator is replaced by those models during the MC analysis, which enables performing expanded MC for accurate yield estimations without running any simulations. To demonstrate the developed tool, three analog circuits were optimized, a single stage-active loaded amplifier, a two stage amplifier, and a voltage comparator. According to the synthesis results, the proposed approach can achieve up to 96.61% reduction in overall execution time (29x speed-up).

In this article, a synthesis methodology for analog circuit design is presented. This methodology utilizes symbolic math tools to systematically and exhaustively search for candidate analog circuits avoiding tedious manual work. The two-port network matrix representation of active devices, such as MOS transistors, paves the way for efficiently using advanced symbolic math toolboxes (e.g., in MAPLE or MATLAB) to automate the generation of new analog circuits and further investigate the effects of nonidealities and parasitics. Using this synthesis methodology new amplifiers, filters, and oscillators can be obtained starting from a predefined structure. This article aims to motivate and provide an overview of the current status of research in this area. In addition, two detailed design examples of a family of differential filters and a family of differential oscillators along with their simulations and measurement results are provided to illustrate and verify the synthesis methodology.

The design process of analog circuits is a challenging issue due to the nonidealities. Thus, analog IC design must be automated to shorten the design time and must be optimized to improve the important performance criteria, such as power dissipation, estimated chip occupation area, etc. In this work, a genetic algorithm (GA)-based approach is proposed for the low-pass filter design of IEEE 802.11n Wireless LAN. The performance criteria of OTA and CCII are modeled with an artificial neural network and transistor sizes of those blocks are determined with GA to improve the performance and to satisfy the constraints. The advantage of the proposed methodology is to eliminate infeasible solutions before starting circuit design by modeling the design constraints according to the transistor sizes allowed by production technology. The performance of the proposed method is tested with 0.18- $\mu \text{m}$ technology in CADENCE environment.

As the 5G era beckons in the world of communication and information technology, there is a surge in demand for battery-operated, mobile wireless devices. These wireless devices which are part of the Internet-of-Things (IoT) framework are required to process data with at most accuracy. With sub-6 GHz 5G networks, the IoT systems must be able to withstand large interferers in order to maintain the fidelity of the message signal. Therefore, the linearity of the analog circuits is inevitably crucial for 5G networks. Thus, analog circuits with high linearity at reduced power consumption is the present-day challenge for implementing battery-powered 5G applications. To address the growing market demand for battery-powered wireless devices, this work proposes an ultra-low-power RF mixer with enhanced linearity suitable for sub-6 GHz 5G applications. The post-layout simulations indicate an IIP3 of 8.63dBm while the conversion gain and double-sideband noise figure (DSB-NF) are 9.5 dB and 12.26 dB respectively at 2.4 GHz. The proposed mixer sources 223.3 $$\mu$$ A from a 1 V power supply. The proposed circuit is characterized by process-voltage-temperature variations, random process and device mismatches, and also for local oscillator feedthrough.

Fault prediction in the analog circuits is a serious problem to be addressed on an immediate basis, as traditionally, the faults in the analog circuits are diagnosed only after their occurrence. Since the outcome of the faults creates highly expensive scenarios in case of the analog circuit industry, there is a need for an effective prediction model that keeps track of the faults prior to their occurrence. Accordingly, this article focuses on the fault prediction model in analog circuits using proposed deep model called, Rider-deep-long short-term memory (LSTM). Here, the significance and precision of the prediction relies on the fault indicator, which is computed based on three distance measures, such as mahalanobis distance, Euclidean distance, and angular distance, and thereby, enables an effective health estimation of the circuit. The estimation is effectively solved using the Rider-deep-LSTM, which is the integration of proposed Rider-Adam algorithm in deep-LSTM, for training the model parameters. The proposed prediction method acquires the Pearson correlation coefficient of 0.9973 and 0.9919 while using the circuits, such as solar power converter and low noise bipolar transistor amplifier.

Ultralow-power sensing with inference functionality embedded in sensor nodes is essential for enabling the emerging pervasive intelligence. For acoustic inference sensing, the feature extraction can take advantage of power-efficient analog circuits. However, the existing solutions have been mostly constrained to linear analog signal processing, which largely limits the achievable power efficiency. In this article, we show that tasks like voice activity detection and keyword spotting can well accommodate analog feature extractor's high nonlinearity, which arises from electronic device physics and circuit design constraints. Applying this principle to a 65-nm CMOS chip implementation, we demonstrate high classification accuracy with nonlinear analog feature extraction consuming only 50 nW. At the end of digital scaling, this study may shed light on the possibility of exploiting the largely relaxed degree of freedom, i.e., linearity, in analog circuit design in the pursuit of extreme power efficiency for designing future inference sensing systems.

This paper presents an electrocardiogram amplifier with operational transconductance amplifier at 0.18 µm. Comb active filters are used for designing of amplifier circuits and the selected frequencies are removed from various signals. The designing of filter circuit is based on only transconductance amplifiers and capacitors are very suitable for implementation of ICs. Different ECG signals 60, 180, 300 and 420 Hz is applied to the analog circuits’ know the working capability of analog circuits. Different ECG parameters are measured with the help of cadence Virtuoso tool, this tool is analog design environment, the performance parameters are bandwidth and gain increases for an increase in bias current.

A low output resistance and high slew rate class-AB flipped voltage follower (FVF) cell is presented in this paper. The proposed FVF cell consists of cascoding transistor which provides the extra gain to the feedback loop and leads to the low output resistance while the bulk-driven transistor acts as an adjustable current source to increase the current driving capability and slew rate. The proposed FVF cell offers numerous advantages such as low output resistance, high current driving capability, wide bandwidth, high symmetrical slew rate and occupies less chip area. The proposed circuit has been designed using Cadence virtuoso tool in 0.18 µm CMOS technology and the post-layout simulation results are presented to validate its performance. To show the performance under extreme conditions, the analysis of the proposed circuit at various corners has also been presented.

This article describes a single-chip analog computer for solving 1-D wave equations. The chip uses switched-capacitor (SC)-based fully differential analog circuits to build a discrete-time but continuous-valued finite difference solver with spatially programmable wave velocity, selectable boundary conditions, and arbitrary input excitation waveforms. Correlated double sampling (CDS) and auto-zero techniques are utilized to minimize the offset and low-frequency noise of the op-amps. Built-in third-order $\Delta $ - $\Sigma $ modulators allow the analog solution to be easily read out by a digital processor. The design was realized in TSMC 180-nm CMOS and has an active area of 3.596 mm $\times3.131$ mm. The solver consumes 560 mW while providing a dynamic range (DR) of 41 dB and a computational bandwidth of either 2.5 MHz (if limited by the analog core) or 0.25 MHz (if limited by the on-chip modulators). Normalized mean squared solution errors for a typical problem (uniform medium with radiation boundary condition) range from 0.3% to 2% (−25 to −17 dB). Measured simulation times are $21\times $ , $5\times $ , and $1.3\times $ faster than CUDA-C code running on a modern GPU (NVIDIA GTX 1080 Ti) and MATLAB or C code running on an 8-core CPU (Intel Xeon Silver 4110 at 2.10 GHz), respectively.

The concept of Precision Agriculture has been conceived several decades ago however, it has never been fully implemented due to several technological constraints, such as the high cost of automated systems. In this paper, a versatile, low-cost and stand-alone sensing node with unique capabilities is presented, suitable for direct soil quality monitoring. The node is equipped with a potentiostat to run electrochemical measurements as well as a circuit for potentiometric measurements, a circuit to accommodate a wide variety of resistance thermometers and a circuit to detect impedance at 1 kHz. All analog circuits feature accuracies of less than 5% with linearity of more than R2 = 0.999. The system is battery-powered and can recharge through a solar panel or a power supply. Bluetooth, WiFi and LoRa communication technologies are supported making the system IoT compatible whilst maintaining a low cost. The designed instrumentation is versatile enough so that it can accommodate other sensors operating under the same principles with different sensitivities, as well as commercial sensors communicating through SPI and I2C protocols. All the modifications to the system can be done through software during sensor calibration.

The range of transmitters, detectors and other components that can be used in optical wireless links means that they can have a wide variety of frequency responses. Both pre- and post- equalization have been used in optical wireless systems to increase data rates. Pre-equalization has the advantage that noise impairments due to equalization can be minimised. However, the variety of pre-equalizer transfer functions, which can be easily created using analog circuits, is limited by the frequency responses of these circuits. Consequently, it may not be possible to equalize some optical wireless links with analog circuit-based pre-equalizers. In this paper a flexible digital pre-equalization scheme that can equalize complex frequency responses is described. The flexibility and the applicability of the scheme is also demonstrated using two example systems, including one that incorporates a fluorescent optical fiber to create a wide-field-of-view receiver for handheld devices. In particular, the bandwidths of the two example systems have been increased to over 500 MHz and to 350 MHz, resulting in at least a three-fold increase in data rate without any post-equalization. The authors believe that this is the first time such significant improvements in on-off-keying data rates have been demonstrated in systems with a relatively complex frequency response and a limited dynamic range.

This paper presents new analog circuits realised using switched-capacitor technique. New phase-shifter, low-pass filter and integrator circuits are proposed employing only a single positive type cu...

In this paper, a systematic approach has been used to apply gm/Id method for the design of Independent Gate (IG) FinFET amplifiers. The design of high-performance amplifiers using gm/Id method has been successfully applied to nanometer devices. IG-FinFETs have been widely used in digital circuit implementations. However, the application of IG-FinFETs in analog circuits is limited and brings many advantages including low power, low voltage operation of transistors. Independent gates of FinFET can receive different voltages that facilitate low voltage operation of the circuit. Simulation-based gm/Id method has been applied to IG-FinFET transistors and a systematic methodology has been developed for the design of IG-FinFET amplifiers. The Berkeley BSIM-IMG 55 nm technology parameters have been used for HSPICE simulations. The designed amplifier has a DC gain of about 45 dB while consuming 6.5 µW from single 1 V power supply.

An analog circuit design methodology based on applications of control theory is the basis for constructing an optimal or quasi-optimal design algorithm. The main criterion for identifying the required structure of the algorithm is the behavior of the Lyapunov function, which was decisive for the circuit optimization process. The characteristics of the Lyapunov function and its derivative are the basis for finding the optimal structure of the control vector that determines the structure of the algorithm. A block diagram of a quasi-optimal algorithm that implements the main ideas of the methodology is constructed, and the main characteristics of this algorithm are presented in comparison with the traditional approach

A general-purpose analog computing method is proposed to compute the continuous-time solutions of nonlinear partial differential equations (PDEs). The discrete-time difference operator in the standard finite difference time domain (FDTD) method is replaced by continuous-time delay operators that can be realized using analog all-pass filters. The resulting spatially discrete time-continuous (SDTC) update equations are realized using analog circuits which compute continuous-time solutions of the PDE with prescribed initial and boundary conditions. The proposed concept is demonstrated in simulation via an integrated circuit (IC) design of a nonlinear acoustic wave equation solver in 180 nm CMOS technology. Analog arithmetic operations (multiply, scale, and add) are realized in parallel using fully differential op-amps and analog multipliers. The proposed IC computes the PDE solution in parallel at 33 discrete spatial points and has a simulated bandwidth and power consumption of approximately 2 MHz and 3 W, respectively. The performance of the IC is simulated using foundry-supplied device models and quantified using i) the mean squared difference between the circuit simulation results and FDTD simulations, and ii) the noise to signal energy ratio. Acceptable accuracy is obtained, with error metric values varying between −7 and −30 dB for various configurations of the problem. Comparison of the custom analog IC simulations with MATLAB- and C-based FDTD code running on a modern workstation shows an expected average speedup of $205\times $ and $140\times $ , respectively.

Layout-dependent effects (LDEs) have become increasingly more important in the synthesis of analog integrated circuits. In this article, a two-phase hybrid sizing method for high-performance analog circuits is proposed. It consists of $g_{m}$ / $I_{D}$ -based device characterization, circuit modeling, sensitivity-based constraints for LDEs, mixed-integer nonlinear programming (MINLP) in the first phase, and many-objective evolutionary algorithm (many-OEA)-based sizing in the second phase. In the first phase, accurate device characterization is handled with little modeling effort thanks to the $g_{m}$ / $I_{D}$ design methodology. Then, the LDE parameters that are linked to the normalized dc current are further optimized with the aid of sensitivity analysis. Thus, a variety of electrical, geometrical, and LDE-related constraints can be conveniently integrated into modeling of the sizing problem. In the second phase, the many-OEA-based sizing refiner can further optimize the LDE parameters by using more detailed layout information via our proposed model. A new floorplan variation scheme is also applied to improve computation efficiency and enhance optimization effectiveness. The experimental results demonstrate high efficacy of our proposed methodology in LDE-aware analog sizing optimization.

Deep learning has achieved excellent results in many fields due to powerful feature extraction and learning ability. In this study, an improved method for analog circuit fault diagnosis based on a deep residual network is presented. The proposed method utilizes a ResNet to extract the performance characteristics of an analog circuit and determine the fault type of a component to realize the fault diagnosis of a circuit. The Short-time Fourier Transform is used to convert the time-domain output signals of a circuit into two-dimensional circuit spectrum maps, which are further used as the ResNet input. The fault diagnostic performance of the proposed method is verified by simulation with the Sallen-key bandpass filter circuit and the Four-opamp biquad high-pass filter circuit. The simulation results show that the proposed method performs well on both test circuits, achieving the diagnostic accuracy of up to 99.1% on the second-mentioned circuit.

Metal-oxide based bipolar Resistive RAM (RRAM) is one of the most promising candidates for the future non-volatile data storage. Due to unique properties e.g., small footprint, ability to modulate resistance states in wide ranges dynamically, hysteresis and CMOS compatibility, RRAM can be a fruitful candidate for analog circuit design. However, the recent literature only scratches the surface of this interesting prospect. In this paper, a single RRAM behavior is studied under temperature, voltage and process variations from an analog design standpoint. A comparative study is performed between two analog circuits namely, Common Source (CS) amplifier and differential amplifier with traditional passive resistors and with passive resistors replaced by RRAM along with two other design examples, namely constant $g_m$ g m biasing circuit and active low-pass filter, where RRAM can be integrated into analog circuits. Our study shows that blind swapping of passive resistors with RRAM in analog circuits can actually degrade the performance metrics. We propose techniques such as usage of RRAM Low Resistance State (LRS) to recover the loss. We also note that hyperbolic I-V characteristics of RRAM can inherently improve the linearity of RRAM based analog designs. Simulation results indicate that RRAM based amplifiers can achieve 2X area reduction, about 1.5X higher bandwidth with only $\approx 9\%$ ≈ 9 % reduction in gain. The resistance modulation property of RRAM is applied to realize a source degenerated amplifier with reconfigurable linearity, to a constant transconductance bias circuit to avoid resistance trimming and to design a programmable active low pass filter.

The electrolyte membrane fuel cell (PEMFC) is characterized by a low and unregulated output voltage; thus, an interface between source and load is required for processing the generated energy by the PEMFC. In this paper, a solution for processing the energy generated by a PEMFC is given. A switching regulator is developed by using a quadratic boost converter with a single switch (QBC-SS). The controller for the QBC-SS is designed using average current-mode (ACM) control, which is easy to implement using analog circuits. The proposed switching regulator ensures high conversion ratios, output voltage regulation, adequate dynamic performance, and stability. On the other hand, a model with static characteristics for the PEMFC electrical behavior is proposed, which can be used for modeling and control purposes. This model consists of three parameters, which are computed using experimental data of the PEMFC stack. A laboratory prototype of 400 W is used to verify the analytical results. As an input source, a PEMFC system is used. The output voltage of the PEMFC stack ranges from 41 V to 24 V, which depends on the generated current. Experimental results applying load step changes and frequency response analysis are shown.

The describing function theory is a powerful mathe matical tool to predict oscillations in non-linear dynam ical systems. This theory is here invoked to design a random signal generator and realized by using analog electronic elements. Then, and according to experimen tal results, histograms of the resultant signal are shown along with the generated signal in the time domain. Fi nally, the proposed electronic circuit is simple and cheap to construct

Conjugated polymers with well-balanced ambipolar charge transport is essential for organic circuits at low cost and large area with simplified fabrication techniques. Aiming at this point, herein, a novel asymmetric thiophene/pyridine-flanked diketopyrrolopyrrole-based copolymer (PPyTDPP–2FBT) is designed and synthesized. Due to the effect of incorporating F atoms on molecular energy alignment and conjugation conformation, the PPyTDPP–2FBT copolymer exhibits typical V-shaped ambipolar field-effect transfer characteristics with well-balanced hole and electron mobilities of 0.64 and 0.46 cm2 V−1 s−1, respectively. Furthermore, organic digital and analog circuits such as inverters and frequency doublers are successfully constructed based on solution-processed films of the PPyTDPP–2FBT copolymers which show a typical circuit operating mode with a high gain of 133 due to the well-balanced electrical properties. In addition, PPyTDPP–2FBT-based devices also demonstrate good stability and batch repeatability, suggesting their great potential applications in organic integrated electronic circuits.

The 5th generation new radio (5G NR) standards create both enormous challenges and potential to address the spatio-spectral-temporal agility of wireless transmission. In the framework of a research unit at TU Ilmenau, various concepts were studied, including both approaches toward integrated circuits and distributed receiver front-ends (FEs). We report here on the latter approach, aiming at the proof-of-principle of the constituting FEs suitable for later modular extension. A millimeter-wave agile multi-beam FE with an integrated 4 by 1 antenna array for 5G wireless communications was designed, manufactured, and verified by measurements. The polarization is continuously electronically adjustable and the directions of signal reception are steerable by setting digital phase shifters. On purpose, these functions were realized by analog circuits, and digital signal processing was not applied. The agile polarization is created inside the analog, real-time capable FE in a novel manner and any external circuitry is omitted. The microstrip patch antenna array integrated into this module necessitated elaborate measurements within the scope of FE characterization, as the analog circuit and antenna form a single entity and cannot be assessed separately. Link measurements with broadband signals were successfully performed and analyzed in detail to determine the error vector magnitude contributions of the FE.

This paper presents a new parametric fault detection (PFD) approach for testing of linear analog circuits. It combines classified frequency-bands with amplitude weighting for fault controllability and test-points selection for fault observability. The test waveform sweeps on an applicable frequency-band instead of the whole band to stimulate parametric faults. The number of required samples is reduced, and the summation of samples from undesired bands is avoided. The test response is compacted for each band generating digital signature. The digital signature curve (DSC) is plotted for each component. A hybrid between MATLAB and PSPICE simulation is used to develop accurate worst case analysis (WCA). The relation between the classified DSC and the accurate WCA results in the enhanced PFD. It is found that the weighted sweeping-sinusoidal waveform is the best selection. The presented approach is applied to different linear analog benchmark circuits and shows the significant PFD improvement compared to previously published works.

Information flow tracking (IFT) is a widely used methodology for ensuring data confidentiality and/or integrity in electronic systems and many such methods have been developed at various software or hardware description levels. Among them, Proof-Carrying Hardware Intellectual Property (PCHIP) introduced an IFT methodology for digital hardware designs described in hardware description languages (HDLs). However, it is not only the digital domain that suffers from the risk of inadvertent information leakage. Indeed, analog signals originating from sources of sensitive information such as biometric sensors, as well as analog circuit outputs could also carry confidential information. Moreover, analog circuits are equally susceptible as their digital counterparts to malicious modifications, known as hardware Trojans, which could introduce covert channels for leaking such confidential information. Furthermore, in analog/mixed-signal circuits, such information leakage channels may cross the analog/digital or digital/analog interface, making their detection even harder and, thereby, intensifying this security concern. As a solution, we introduce a PCHIP-based methodology which enables systematic formal evaluation of information flow policies in analog/mixed-signal designs. This solution can reason on analog designs described at the transistor-level or at the block-level, where an abstract model of the analog circuit is considered. Additionally, it can handle analog circuit models developed in Verilog-A or Verilog-AMS, thereby enabling the use of circuit models developed in these HDLs for IFT purposes. By integrating IFT across the digital and analog domains, the proposed solution is able to detect sensitive data leakage from the digital domain to the analog domain and vice-versa, without requiring any modification of the current analog/mixed-signal circuit design flow.

Editor’s notes: This article presents a novel circuit structure of an arbitrary-order fracmemristor, called ladder scaling fracmemristor. This circuit structure shows that it is possible to realize a second emerging circuit structure of the fractional-order memristor in the form of an analog circuit. — Binoy Ravindran, Virginia Tech

Smal, Alexander Sergeevich Circuitry of analog devices: guidelines for coursework for students of the specialty 1–36 04 02 "Industrial electronics"

Soft fault diagnosis has been validated as a very challenging problem in analog circuits. In order to improve the generalization ability and close to the practical application of fault diagnosis models, a novel method for obtaining a large number of training samples in soft fault interval is proposed in the present work. Training samples are randomly generated in the interval of soft fault to adapt the continuously change of component parameters. Limits of experimental conditions, lead to the limited number of samples labeled by experts, so that training samples are classified using the semi-supervised support vector machine (S3VM) algorithm. Manifold learning algorithm has been used for the feature extraction and the dimension reduction of soft fault time domain response data in analog circuits. Then the semi-supervised Gaussian mixture model (SGMM) is applied to cluster decision trees. Finally, the S3VM classification is used for the soft fault diagnosis in analog circuits. Experimental results show that the proposed method can be utilized in the single and double soft fault diagnosis of analog circuits. It is observed that the S3VM method is extremely significant as a guide in actual engineering applications, although the diagnosis rate is slightly less than the fixed-parameter offset soft faults.

This brief presents a capacitor-less digital low-dropout (DLDO) regulator, which has low steady-state voltage ripples ( $V_{RIPP}$ ) and low output noise, suitable for driving analog circuits in system-on-chip devices. To reduce $V_{RIPP}$ , a steady-state control based on $\Delta \Sigma $ modulation and a clock multiplication technique are proposed. Thanks to the $\Delta \Sigma $ operation, the proposed DLDO generates noise-shaped output voltage ( $V_{OUT}$ ), reducing $V_{RIPP}$ and improving its noise performance without using an output capacitor. The $\Delta \Sigma $ -modulator-based controller is activated just during the steady state, triggered by a lock detector, which continuously tracks $V_{OUT}$ and compares it to a reference $V_{REF}$ . During the steady state, a cyclic time-to-pulse converter and a clock combiner generate an oversampling clock for the controller. The proposed DLDO was fabricated in a 110-nm CMOS process with an active area of 0.07 $mm^{2}$ . The measurement results demonstrate that at $V_{OUT} = 0.5$ V, $V_{DD} = 0.6$ V, and $I_{LOAD} = 500\,\,\mu \text{A}$ , the proposed DLDO achieves $V_{RIPP}$ , 17.5 dB of power supply rejection (PSR) at 1 MHz, and $-151\,\,\text{V}^{2}rms/$ Hz (dB) of power-spectral density at 51.2 kHz. Furthermore, the proposed DLDO achieves 99.77% of current efficiency and 0.25 mV/mA of load regulation while driving the maximum $I_{LOAD}$ of 40 mA.

Fault diagnosis of analog circuit is critical to improve safety and reliability in electrical systems and reduce losses. Traditional fault diagnosis methods of analog circuit usually rely on the hand design feature extractor and can not generalize well to other diagnosis domains. To address these issues, an end-to-end denoising autoencoder (EEDAE)-based fault diagnosis approach is proposed. The proposed approach includes denoising autoencoder (DAE) and a softmax classifier. The DAE is designed to automatically extract fault features from the raw time series signals without any signal processing techniques and diagnostic expertise, and then the softmax classifier is used to classify the fault mode of analog circuits. Specifically, we design a novel loss function by jointly minimizing reconstruction loss and classification loss to improve training efficiency. The proposed approach just has one training stage, in which the encoder, decoder, and classifier are trained simultaneously. The experimental results demonstrate that compared with traditional methods, the proposed method has higher accuracy and lower requirements on data.

The intrinsic gain is a key metric in analog electronics, it is the highest gain that can be obtained for an amplifier in the transistor configuration. However, there lack the demonstration of the intrinsic gain with different parameters comprehensively, they often focus on one or two features. In this work, we fabricated organic thin film transistors (OTFTs) with two types of semiconducting material to compare the effect of mobility on intrinsic gain and varied structural parameters such as active layer thickness and channel length to explore the impacts of those factors. We found that the intrinsic gain does not have much correlation with the mobility and the contact resistance. In addition, the intrinsic gain decreases as the channel length decreases, the increment of the gate voltage, and the decrease of the thickness of the active layer. The better understanding of different impacts on the intrinsic gain on OTFTs could provide indication for its real application design of organic circuit to obtain higher gain value, which is needed in the future amplifier processing. We fabricated organic thin film transistors (OTFTs) with indacenodithiophene-co-benzothiadiazole (IDTBT) and Poly(N,N′-bis-4-butylphenyl-N,N′-bisphenyl)benzidine (Poly-TPD) in order to investigate influences of fundamental parameters on intrinsic gain. We varied structural parameters such as active layer thickness and channel length on fabrication of devices. The mobility has extracted and compared with fundamental parameters. Even though devices with Poly-TPD showed lower mobility, but it has higher intrinsic gain. While, IDTBT-based devices showed lower intrinsic gain, even though they have much higher mobility than Poly-TPD-based device. As a result, we confirmed that thick active layer, long channel length, and small gate voltage are favorable to obtaining high intrinsic gain in OTFTs. We suggest that OTFT is a suitable configuration for exploration the intrinsic gain.

We present a tool framework to compile and program mixed-signal circuits and systems on Floating-Gate (FG) based mixed-signal System-on-Chips (SoC) consisting of a digital processor and Field Programmable Analog Array (FPAA) fabric. We have modified the configuration of Verilog-to-Routing (VTR) to cover analog circuits and developed a tool called vpr2swcs to create the list of FG switches, that is going from a high level block description of the system to the addresses and bias values on the SoC. This tool enables users to generate macro blocks and customize block location while designing mixed-signal systems on the FPAA and also enables using routing fabric, composed of FGs, for Vector Matrix Multiplication (VMM), a computing element for an analog neural network. The paper demonstrates system level examples using this tool flow, where the experimental results have been proved in other publications.

International audience; Cyber physical systems are built upon digital and analog circuits, making it necessary to handle different models of computation during their design and verification (e.g., by simulation). When designing these systems, an important aspect to consider is the causality between the different domains. For this, we introduce a new model-driven framework able to identify causality problems and to suggest a valid schedule between the analog and digital domains. Once a valid schedule has been computed, our framework can generate cycle and bit accurate virtual prototypes (in SystemC/SystemC AMS) from high-level SysML models.

Software-programmable analog computing is proposed for power- and area-efficient acceleration of computational electromagnetics. All-pass filters are employed to realize a continuous-time finite-difference time-domain (FDTD) algorithm. A CMOS realization of an analog computer (AC) that solves the 1-D wave equation using this time-continuous FDTD algorithm at an equivalent temporal update rate of 625 MHz is reported (180-nm CMOS, chip area of 4 mm2, supply voltage = 1.8 V, and power = 200 mW). The AC operates at up to 30 MHz over 18 discrete spatial points. Analog arithmetic operations (multiply and add) are realized in parallel using op-amps with gain–bandwidth product > 500 MHz. Computational grid boundaries can be configured to simulate multiple propagation scenarios. The AC is calibrated using a stochastic optimization algorithm. The normalized mean squared error of the AC varies between −10 and −20 dB within the computational grid. The power- and area-normalized performance of the design improves on earlier integrated ACs by up to three orders of magnitude. The chip is also 26 $\times $ faster than a C-based software FDTD solver running on an Intel Xeon CPU and $420\times $ faster than CUDA FDTD code running on an NVIDIA GeForce GTX 1080 Ti GPU, albeit at lower accuracy (~6 bits). Finally, the AC is $2.8\times $ faster than a digital systolic array FDTD processor realized using a Xilinx RFSoC ZCU1275 and has 15 $\times $ better power efficiency (computations/W).

In the field of low power VLSI, the charge recovery property of adiabatic logic has been liked by the VLSI researchers. And this stimulates the research of various charge recovery techniques for low power computation. The applications of adiabatic logic in digital circuits are well understood, whereas mixed signals and analog circuits are yet to be explored. In this work, the author presents a wave shaping diode-based adiabatic logic (WSDAL) driven strong ARM comparator. The proposed ARM comparator consumes a power of 0.46 µW as compared to 14.41 µW and 8.77 µW as that of traditional strong ARM and adiabatic driven strong ARM, respectively. The reduction in power dissipation is achieved by three ways, (1) the proposed design consists of WSDAL based invertor for SR latch inputs that reduces the power dissipation up to a great extent by charge recycling through PCb (power clock bar). (2) The magnitude of PCb is half as that of PC (power clock), which reduces the node voltage difference and ultimately reduces the power dissipation, (3) the leakage and short circuit components of current get reduced utilizing PC as a sinusoidal supply. The proposed design also shows better thermal stability with varying temperature conditions.

Active capacitors with long lifetime film capacitors can be adopted to replace short lifetime electrolytic capacitors to improve the reliability of the power converter. However, the conventional active capacitor suffers from the complicated control method or the need for an expensive current sensor. Based on the derived mathematical equations, a novel Ripple Cancellation Control (RCC) method for the active capacitor is proposed. The proposed RCC method is simple and can be easily realized by using analog circuits. Also, it can be applied to active capacitors implemented by different circuit topologies. Besides, a new approach for developing the mathematical model of the active capacitors implemented by different circuit topologies are also proposed. The energy storage capability and the impedance analysis by using the developed mathematical model are presented to verify the performance of the active capacitors with the proposed RCC method. Computer simulations and the hardware results are presented to validate the accuracy of the mathematical model as well as the performance of the proposed RCC method.