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This paper proposes a design-oriented DC model for MOS transistors in advanced nanometric technologies, based on only six parameters. The proposed model is based on the inversion charge and includes the main short-channel effects for accurately describing the behavior of the transistor DC drain current in all regions (linear to saturation) and regimes of operation (weak to strong inversion). The proposed model is critically compared to existing inversion charge-based models, highlighting the main limitations of previous models presented in the literature and the advantages and disadvantages of our proposal. Then, regarding the model implementation, previously presented inversion charge-based models require a numerical solver to link the transistor’s DC current to its DC node voltages. In this work, we propose an innovative approach to model implementation via the analytical approximation of the Lambert function’s principal branch. Thanks to this approximation, the proposed design-oriented model offers for the first time an analytical single-piece expression of the drain current as an explicit function of the transistor node voltages. The validity of both the proposed transistor DC model and its analytical single-piece implementation is confirmed through simulation and measurement results, using the industrial production-level model UTSOI2 as a reference. The evaluations were conducted on MOS transistors with lengths of 30nm, 60nm, and 150nm in STMicroelectronics 28nm FD-SOI CMOS technology, to validate our results in minimum length, intermediate length, and long transistors in the selected technology. The proposed model achieves an average error of less than 6% in drain current evaluation compared to industry-standard models such as UTSOI2, while significantly reducing computational complexity.

This paper presents a novel charge-based MOSFET model, denoted ACM2, including velocity saturation and drain-induced barrier lowering. Employing the proposed model, all the DC characteristics (currents and charges) and the small-signal equations can be expressed as single-piece expressions valid in all inversion (weak, moderate, and strong) regions. When applied to bulk technology, ACM2 has 5 DC parameters, and an extra parameter is included for SOI technologies to account for back gate bias. Straightforward procedures are provided for extracting the short-channel parameters associated with velocity saturation and back gate bias. Experimental results demonstrate that the DC and small-signal characteristics of the ACM2 model match the silicon measurements in bulk and SOI technologies, with typical errors of less than $20~\%$ in the DC currents and $30~\%$ in the transconductances. The validity of the model is further verified with two design examples. Firstly, simulations of a CMOS inverter in a 130 nm bulk technology show similar results using the PSP or ACM2 models. Then, an RF design example is provided. The ACM2 model is employed to design a 2.4 GHz low-noise-amplifier in a 28 nm FD-SOI CMOS technology. Obtained results in terms of $S_{11}$ , $S_{21}$ , NF, and IIP3 are consistent with simulations using the complete UTSOI2 model provided in the technology design kit.

The integration of Single-Photon Avalanche Diodes (SPADs) in CMOS Fully Depleted Silicon-On-Insulator (FD-SOI) technology under a buried oxide (BOX) layer and a silicon film containing transistors makes it possible to realize a 3D SPAD at the chip level. In our study, a nanostructurated layer created by an optimized arrangement of Shallow Trench Isolation (STI) above the photosensitive zone generates constructive interferences and consequently an increase in the light sensitivity in the frontside illumination. A simulation methodology is presented that couples electrical and optical data in order to optimize the STI trenches (size and period) and to estimate the Photon Detection Probability (PDP) gain. Then, a test chip was designed, manufactured, and characterized, demonstrating the PDP improvement due to the STI nanostructuring while maintaining a comparable Dark Count Rate (DCR).

This paper presents a 7-parameter analytical model of the MOS transistor based on the inversion charge targeted at the development of simplified analytical circuit design methodologies that take into account the physics of the MOS transistor. The proposed design-oriented model allows for the first time to describe both the main short-channel effects of advanced nanometric technologies and the dependence of the transistor drain current on the drain voltage, while the model remains valid for all bias regimes (from weak to strong inversion) and for all operating regions (linear and saturated). A simple procedure based on the device physics is proposed to estimate the transistor model parameters for a given technology. Furthermore, analytical expressions of the current derivatives are developed targeting different design scenarios. The accuracy of the proposed model is validated by direct comparison to silicon measurements of N-MOS transistors in 28 nm FD-SOI technology for channel width of $1~\mu \text{m}$ and channel lengths of 30 nm, 60 nm and 150 nm, and also to simulations performed with an industry-standard compact model.

Wireless Body Area Networks (WBANs) are a fast-growing field fueled by the number of wearable devices developed for countless applications appearing on the market. To enable communication between a variety of those devices, the IEEE 802.15.6 standard was established. However, this standard has some intrinsic limitations in addressing the heterogeneity of the network nodes in terms of activity, data rates (from less than bit/s to multiple Mbit/s), energy availability, form factor, and location on, around or inside the body. To address these concerns, an alternative model is proposed that could serve as an extension of the IEEE 802.15.6 Standard. At its core is an adaptive and low-overhead synchronization scheme based on heartbeat sensing. This forms the base for a TDMA-based (Time Division Multiple Access) Media Access Control (MAC) protocol dedicated to multi-tier networks. While this effort focuses specifically on Capacitive Body-Coupled Communication (C-BCC), other physical layers can be easily incorporated as well. Based on these premises, this paper compares various random-access slot allocation approaches to accommodate the multiple data rates matching the system requirements, while incorporating a duty-cycling strategy anchored by heartbeat detection. This work proposes a novel, flexible, and robust solution, making use of heartbeat synchronization and addressing the corresponding challenges. It efficiently interconnects multiple device types over a wide range of data rates and targets a mesh of stars topology. At the cost of an increased communication latency, the proposed protocol outperforms the IEEE 802.15.4 MAC standard in terms of energy efficiency by a factor of at least 12x in a realistic scenario.

In the above article [1], equations (33) and (36) had a typing error. The correct equations are:

An ultrafast Active Quenching—Active Reset (AQAR) circuit is presented for the afterpulsing reduction in a Single Photon Avalanche Diode (SPAD). The proposed circuit is designed in a 28 nm Fully Depleted Silicon On Insulator (FD-SOI) CMOS technology. By exploiting the body biasing technique, the avalanche is detected very quickly and, consequently, is quenched very fast. The fast quenching decreases the avalanche charges, therefore resulting in the afterpulsing reduction. Both post-layout and experimental results are presented and are highly in accordance with each other. It is shown that the proposed AQAR circuit is able to detect the avalanche in less than 40 ps and reduce the avalanche charge and the afterpulsing up to 50%.

While there exists a wide variety of radio frequency (RF) technologies amenable for usage in Wireless Body Area Networks (WBANs), which have been studied separately before, it is currently still unclear how their performance compares in true on-body scenarios. In this paper, a single reference on-body scenario—that is, propagation along the arm—is used to experimentally compare six distinct RF technologies (between 420 MHz and 2.4 GHz) in terms of path loss. To further quantify on-body path loss, measurements for five different on-body scenarios are presented as well. To compensate for the effect of often large path losses, two mitigation strategies to (dynamically) improve on-body links are introduced and experimentally verified: beam steering using a phased array, and usage of on-body RF repeaters. The results of this study can serve as a tool for WBAN designers to aid in the selection of the right RF frequency and technology for their application.