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Switching lattices are two-dimensional arrays composed of two or four-terminals switches organized as a crossbar array. The idea of using regular two-dimensional arrays of switches for Boolean function implementation was proposed by Akers in 1972. Recently, with the advent of a variety of emerging nanoscale technologies, lattices have found a renewed interest. Emerging technologies allow more complex function integration, thanks to their smaller sizes and advanta geous properties such as zero leakage current, capability to retain data when in power-off state, and almost unlimit edendurance, to name just a few appealing features. Also, implementation of new computing paradigms combining memory and logic becomes possible. However, emerging technologies show a non-negligible defect ratio and higher sensitivity to process and environment variations. The reliability challenges in adopting these technologies need to be investigated. In this paper, we analyze the resilience of switching lattices to stuck-at-fault model (SAF). We first identify the critical switches through an elaborated sensitivity methodology and extensive analysis of the lattice. Next, we propose several techniques to improve lattice resilience in the face of these types of faults, that can be implemented after lattice logic optimization steps. [ABSTRACT FROM AUTHOR]

This paper presents an overview of test and reliability approaches for approximate computing architectures. We focus on how specific methods for test and reliability can be used to improve the characteristics of approximate computing in terms of power consumption, area, life expectancy and precision. This paper does not address specification and design of approximate hardware/software/algorithms, but provides an in-depth knowledge on how the reliability and test related techniques can be efficiently used to maximize the benefits of approximate computing. [ABSTRACT FROM AUTHOR]

Three-dimensional (3D) integration is a key technology for systems whose performance and power requirements cannot be achieved by traditional silicon technologies. 3D chips consist of two or more stacked silicon dies connected by short inter-die wires called Thru-Silicon-Vias (TSVs). Despite its potential, the poor reliability and yield, thermal management and testing issues remain major challenges of 3D integration. We address the TSV interconnect test challenge of 3D chips by using Interconnect Built-In Self-Test ( IBIST) techniques. The proposed test strategy must sensitize structural faults like opens and shorts, and delay faults due to crosstalk. A possible approach is the well-known Maximum Aggressor Fault (MAF) model. Unfortunately, this model is too conservative and it leads to long test sequences and non-negligible hardware costs. Therefore, we present an alternative solution: the K-Aggressor Fault (KAF) model. In our model, aggressors of victim wires are neighboring wires within an optimized distance order K. The aggressor order K is technology-dependent and is determined such that the test times are minimal and the fault coverage is maximal. KAF-based IBIST implementation targeting TSV tests occupies three times less area than similar MAF-/marching-based implementations. We also propose a reconfigurable KAF-based IBIST implementation where tests can be performed using different aggressor orders K. Although the reconfigurable IBIST area is significant, interconnect tests during system lifetime can be performed using lower aggressor orders, reducing test duration and improving TSV availability. [ABSTRACT FROM AUTHOR]

Three dimensional (3D) integrated systems become a reality nowadays, as Thru-Silicon-Via (TSV) technologies mature. 3D integration promises significant performance and energy efficiency improvements by reducing the signal travel distances and integrating more capabilities on a single chip. High integration costs, thermal management, and poor reliability and yield are major challenges of TSV based 3D chips. High structural and parametric fault rates due to manufacturing defects makes it difficult to achieve high interconnect yield using only spare-based repair solutions. In this paper we address the TSV yield issue by implementing the inter-die links of 3D chips as Configurable fault-tolerant Serial Links (CSLs). When there are not enough available functional TSVs, faults are tolerated by performing data serialization. CSLs help reduce chip costs by improving the TSV yield with very few or no spares at all. For 3D Networks-on-Chip (3D NoCs) we show that the CSL yield improvement comes with moderate area overheads (~12-26%) and small performance penalties (less than 5% average latency overhead). [ABSTRACT FROM AUTHOR]

Abstract: Existing routing algorithms for 3D deal with regular mesh/torus 3D topologies. Today 3D NoCs are quite irregular, especially those with heterogeneous layers. In this paper, we present a routing algorithm targeting 3D networks-on-chip (NoCs) with incomplete sets of vertical links between adjacent layers. The routing algorithm tolerates multiple link and node failures, in the case of absence of NoC partitioning. In addition, it deals with congestion. The routing algorithm for 3D NoCs preserves the deadlock-free propriety of the chosen 2D routing algorithms. It is also scalable and supports a local reconfiguration that complements the reconfiguration of the 2D routing algorithms in case of failures of nodes or links. The algorithm incurs a small overhead in terms of exchanged messages for reconfiguration and does not introduce significant additional complexity in the routers. Theoretical analysis of the 3D routing algorithm is provided and validated by simulations for different traffic loads and failure rates. [Copyright &y& Elsevier]

Semantic segmentation of images is essential for many applications including autonomous driving and modern DNNs now achieve high accuracy. Automotive systems are safety critical systems and in turn they must comply with safety standards, requiring at least hardware fault detection capability. Small embedded applications also require some level of fault tolerance, while operating with a tight power budget. In this paper, we first present a detailed analysis of the effects of faults using Google's DeepLabV3+ network processing an industrial data-set. Further to that, two techniques to mitigate hardware faults are proposed. The first one is a symptom-based fault detection algorithm shown to detect > 99% of critical faults with zero false positives and a compute overhead of 0.2%. The second one is a simpler technique, using a clipped ReLU activation function, to quickly mask over 99% of the critical faults in the activation values. • New work reporting on faults on DNN image segmentation. • Techniques applicable to autonomous driving. • Detailed analysis of faults from multiple angles. • Solutions have low compute overhead. [ABSTRACT FROM AUTHOR]

Beyond CMOS, new technologies are emerging to extend electronic systems with features unavailable to silicon-based devices. Emerging technologies provide new logic and interconnection structures for computation, storage and communication that may require new design paradigms, and therefore trigger the development of a new generation of design automation tools. In the last decade, several emerging technologies have been proposed and the time has come for studying new ad-hoc techniques and tools for logic synthesis, physical design and testing. The main goal of this project is developing a complete synthesis and optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. New models for diode, FET, and four-terminal switch based nanoarrays are developed. The proposed methodology implements logic, arithmetic, and memory elements by considering performance parameters such as area, delay, power dissipation, and reliability. With combination of logic, arithmetic, and memory elements a synchronous state machine (SSM), representation of a computer, is realized. The proposed methodology targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories. The results of this project will be a foundation of nano-crossbar based circuit design techniques and greatly contribute to the construction of emerging computers beyond CMOS. The topic of this project can be considered under the research area of “Emerging Computing Models” or “Computational Nanoelectronics”, more specifically the design, modeling, and simulation of new nanoscale switches beyond CMOS. [ABSTRACT FROM AUTHOR]

An online fault tolerant routing algorithm for 2D mesh Networks-on-Chip is presented in this work. It combines an adaptive routing algorithm with neighbor fault-awareness and a new traffic-balancing metric. To be able to cope with runtime permanent and temporary failures that may result in message corruption, message loss or deadlocks, the routing algorithm is enhanced with packet retransmission and a new message recovery scheme. Simulation results, for various network sizes, different traffic patterns, under an unconstrained number of node and link faults, temporary and/or permanent, demonstrate the scalability and efficiency of the proposed algorithm to tolerate multiple failures likely encountered in deep submicron technologies. As the experiments have shown, the proposed algorithm maintains high reliability of more than 97.68% for a 2D mesh network of 16 x 16 and in the presence of 384 simultaneous link faults. For the same network and in the extreme scenario of 103 routers being simultaneously faulty, the obtained reliability is more than 93.40%. [ABSTRACT FROM AUTHOR]

Modern CMOS technologies such as FDSOI are affected by severe aging effects that do not only depend on physical issues related to nanoscale technologies, but also on the circuit environment and its run-time activity. Therefore it is extremely difficult to reliably establish a-priori guard bands for Critical Path estimations, usually leading to both large delay penalties (and therefore loss of performances) or too short operating lifetime. In this paper, we propose an approach that uses Machine Learning techniques to obtain reliable predictions of the aging of the Near Critical Paths. Starting from a limited set of measurements and simulation data, our framework is able to accurately estimate Critical Path delay degradation in time depending on physical parameters, environment conditions and circuit activity. Further to that, the corresponding regression models are applied to obtain dynamic aging-aware Operating Performance Point selection strategies. • Modern technologies suffer from aging effects with a strong dependence on activity. • We propose a Machine Learning framework able to predict FDSOI workload-aware aging. • The ML framework is validated against known foundry gate-level data. • The framework is applied to representative Circuits with different workload. • We propose a dynamic aging-aware Operating Performance Point adaptation. [ABSTRACT FROM AUTHOR]

• Scaling and controlling the synaptic current is indispensable for integrating emerging non-volatile memories (eNVMs) into different grids and design choices of advanced CMOS Technology nodes. • The maximum current scaling down factor depends on the leakage current of the spiking neuron, and the saturation conditions of the current source of the transconductance amplifier. • The fan-in of the 28 nm FD-SOI analog spiking neuron depends on the eNVMs technology, the width and amplitude of input spikes, the firing threshold of the neuron, and the current scaling down factor. • The tunable and versatile current attenuator allows the integration of various eNVMs into 28 nm FD-SOI technology based analog spiking neural networks. In this work we report a study and a co-design methodology of an analog SNN crossbar output circuit designed in a 28 nm FD-SOI technology node that comprises a tunable current attenuator and a leak-integrate and fire neurons that would enable the integration of emerging non-volatile memories (eNVMs) for synaptic arrays based on various technologies including phase change (PCRAM), oxide-based (OxRAM), spin transfer and spin orbit torque magnetic memories (STT, SOT-MRAM). Circuit SPICE simulation results and eNVM experimental data are used to showcase and estimate the neurons fan-in for each type of eNVM considering the technology constraints and design trade-offs that set its limits such as membrane capacitance, supply voltage, leakage, etc. [ABSTRACT FROM AUTHOR]

This article proposes a technique to improve the dependability of circuits under energetic particle irradiation by resizing transistors in the most critical paths. First, the SET vulnerability of a mapped circuit is analyzed to identify the most sensitive nodes. The sensitivity of the circuit is defined by the logical and electrical masking. Once the most critical nodes are selected, a transistor sizing algorithm is able to resize the pull-up and pull-down transistors separately. The asymmetric resizing offers interesting area and performance trade-off in comparison with gate sizing and gate duplication techniques. Results show very small area and performance penalties for circuits operating at ground level for a 130-nm technology process. [ABSTRACT FROM AUTHOR]