Search

A 1.2 V 1.33Gb/s/pin 8Tb NAND flash memory multi-chip package incorporating 16-die stacked 512-Gb NAND flash memories and F-Chip is presented. To meet the performance requirements of storage devices for higher capacity and faster data throughput, the 2nd generation F-Chip is developed. The F-Chip presents a dual bi-directional transceiver architecture including data retiming and training techniques to adaptively improve signal integrity. Besides, the F-Chip supports 1.2 V I/O for low power storage applications. This work, as a result, shows 33% improvement of eye-opening performances and 41% reduction of I/O power consumption compared to the previous generation.

—We describe a digitally controlled oscillator (DCO) which compensates the frequency variations for process, voltage, and temperature (PVT) variations with an accuracy of ±2.6% at 2.5 GHz. The DCO includes an 8 phase current-controlled ring oscillator, a digitally controlled current source (DCCS), a process and temperature (PT)-counteracting voltage regulator, and a bias current generator. The DCO operates at a center frequency of 2.5 GHz with a wide tuning range of 2.2 GHz to 3.0 GHz. At 2.8 GHz, the DCO achieves a phase noise of -112 dBc/Hz at 10 MHz offset. When it is implemented in an all-digital phase-locked loop (ADPLL), the ADPLL exhibits an RMS jitter of 8.9 ps and a peak to peak jitter of 77.5 ps. The proposed DCO and ADPLL are fabricated in 65 nm CMOS technology with supply voltages of 2.5 V and 1.0 V, respectively. Index Terms—Digitally controlled oscillator, ring oscillator, PVT compensated DCO, PT-counteracting voltage regulator, all-digital phase-locked loop

This paper reports a high resolution LC-based digitally controlled oscillator (DCO) using novel quadruple resolution varactor. Proposed DCO has a high frequency resolution and a wide tuning range of 2.2 GHz with a low phase noise at 5.6 GHz. A process and temperature invariant quadruple resolution varactor is proposed to achieve the finest frequency resolution. The proposed varactor achieves one fourth capacitance of a fine varactor, and therefore DCO achieves a very fine frequency resolution with low phase noise. Also, the diode connected circuit makes the proposed varactor robust from the process and temperature variations. The DCO implemented in 0.13 μm CMOS process operates from 3.4 GHz to 5.6 GHz with a resolution from 260 Hz to 0.93 kHz by consuming a power from 5.5 mW to 3.2 mW, respectively. The designed DCO achieves a low phase-noise of −118 dBc/Hz at 1 MHz offset.

This paper presents a 1.2 V pseudo differential, symmetric CMOS Operational Transconductance Amplifier (OTA) by using linearity improvement method for ultra-high frequency (UHF) OTA-C filters. Simulation results show a unity gain bandwidth of 1.2 GHz and a transconductance of 2.15 mS with a good linearity of 7dBm. The power consumption of the proposed OTA is 1.1 mW. The proposed OTA is used to design a 9th order 400 MHz chebyshev I low-pass filter by using 0.13 μm technology. This filter has an attenuation of 30 dB at 600 MHz and it consumes only 13 mW.

In this paper, a 1.2 V novel pseudo differential, symmetric CMOS Operational Transconductance Amplifier (OTA) by using linearity improvement method is presented for Ultra-High Frequency (UHF) OTA-C filter applications. Simulation results show a unity gain bandwidth of 1.2 GHz and a transconductance of 2.15 mS with a good linearity of 7dBm. The power consumption of the proposed OTA is 1.1 mW. The proposed OTA is used to design a 9th - order 400 MHz chebyshev I low-pass filter by using 0.13 ?m technology. This filter has an attenuation of 30 dB at 600 MHz and it consumes only 13 mW.