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1. Antiferroelectric negative capacitance from a structural phase transition in zirconia

2. Antiferroelectric negative capacitance from a structural phase transition in zirconia

3. A tunnel FET compact model including non-idealities with verilogy implementation

5. Trap assisted tunneling and its effect on subthreshold swing of tunnel field effect transistors

13. Strained-[Si.sub.1-x][Ge.sub.x]/Si band-to-band tunneling transistors: impact of tunnel-junction germanium composition and doping concentration of switching behavior

14. A simple semiempirical short-channel MOSFET current-voltage model continuous across all regions of operation and employing only physical parameters

15. MOSFET performance scaling - part II: future directions

16. MOSFET performance scaling - part I: historical trends

18. In situ cleaning effect on the electrical properties of Ge MOS devices by Ar gas anneal

19. The electrical properties of HfO[sub 2] dielectric on Germanium and the substrate doping effect

21. Impact of ion implantation damage and thermal budget on mobility enhancement in strained-Si N-channel MOSFETs

22. A physically based analytical model for the threshold voltage of strained-Si n-MOSFETs

23. Mobility enhancement in dual-channel P-MOSFETs

24. Sensitive strain measurements of bonded SOI films using moire

26. Supply-voltage optimization for below-70-nm technology-node MOSFETs

27. Inverse modeling of sub-100 nm MOSFETs using I-V and C-V

29. A Density Metric for Semiconductor Technology [Point of View]

34. Parasitic dipolar gain reduction and the opotimization of 0.25-(um) partially depleted SOI MOSFET's

35. Auger generation as an intrinsic limit to tunneling field-effect transistor performance.

36. Use of focused-ion-beam and modeling to optimize submicron MOSFET characteristics

37. Effect of floating-body charge on SOI MOSFET design

38. Back-gated CMOS on SOIAS for dynamic threshold voltage control

39. LOCOS-induced stress effects on thin-film SOI devices

40. Investigation of Si/SiGe-based FET geometries for high frequency performance by computer simulation

42. An accurate gate length extraction method for sub-quarter micron MOSFET's

44. Theoretical analysis and modeling of submicron channel length DMOS transistors

45. Channel profile engineering for MOSFET's with 100 nm channel lengths

46. A study of deep-submicron MOSFET scaling based on experiment and simulation

47. Measurement and modeling of self-heating in SOI nMOSFET's

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