282 results on '"Antonino Tumeo"'
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2. ICED: An Integrated CGRA Framework Enabling DVFS-Aware Acceleration.
3. Towards Automated Generation of Chiplet-Based Systems Invited Paper.
4. AXI4MLIR: User-Driven Automatic Host Code Generation for Custom AXI-Based Accelerators.
5. FuseIM: Fusing Probabilistic Traversals for Influence Maximization on Exascale Systems.
6. Analyzing inference workloads for spatiotemporal modeling.
7. VecPAC: A Vectorizable and Precision-Aware CGRA.
8. Towards On-Chip Learning for Low Latency Reasoning with End-to-End Synthesis.
9. High-Level Synthesis of Irregular Applications: A Case Study on Influence Maximization.
10. ML-CGRA: An Integrated Compilation Framework to Enable Efficient Machine Learning Acceleration on CGRAs.
11. Data Transfer Optimizations for Host-CPU and Accelerators in AXI4MLIR.
12. SO(DA)2: End-to-end Generation of Specialized Reconfigurable Architectures (Invited Talk).
13. From High-Level Frameworks to custom Silicon with SODA.
14. An MLIR-based Compiler Flow for System-Level Design and Hardware Acceleration.
15. SODA Synthesizer: An Open-Source, Multi-Level, Modular, Extensible Compiler from High-Level Frameworks to Silicon.
16. Accelerating Random Forest Classification on GPU and FPGA.
17. VWC-BERT: Scaling Vulnerability-Weakness-Exploit Mapping on Modern AI Accelerators.
18. DRIPS: Dynamic Rebalancing of Pipelined Streaming Applications on CGRAs.
19. ASAP: automatic synthesis of area-efficient and precision-aware CGRAs.
20. The SODA approach: leveraging high-level synthesis for hardware/software co-design and hardware specialization: invited.
21. Bridging Python to Silicon: The SODA Toolchain.
22. End-to-End Synthesis of Dynamically Controlled Machine Learning Accelerators.
23. Svelto: High-Level Synthesis of Multi-Threaded Accelerators for Graph Analytics.
24. AXI4MLIR: User-Driven Automatic Host Code Generation for Custom AXI-Based Accelerators.
25. Fused Breadth-First Probabilistic Traversals on Distributed GPU Systems.
26. High-Level Synthesis of Parallel Specifications Coupling Static and Dynamic Controllers.
27. OpenCGRA: Democratizing Coarse-Grained Reconfigurable Arrays.
28. Towards Automatic and Agile AI/ML Accelerator Design with End-to-End Synthesis.
29. Automated Generation of Integrated Digital and Spiking Neuromorphic Machine Learning Accelerators.
30. DynPaC: Coarse-Grained, Dynamic, and Partially Reconfigurable Array for Streaming Applications.
31. AURORA: Automated Refinement of Coarse-Grained Reconfigurable Accelerators.
32. Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications.
33. AWB-GCN: A Graph Convolutional Network Accelerator with Runtime Workload Rebalancing.
34. SODA: a New Synthesis Infrastructure for Agile Hardware Design of Machine Learning Accelerators.
35. OpenCGRA: An Open-Source Unified Framework for Modeling, Testing, and Evaluating CGRAs.
36. cuRipples: influence maximization on multi-GPU systems.
37. Invited: Software Defined Accelerators From Learning Tools Environment.
38. EXAGRAPH: Graph and combinatorial methods for enabling exascale applications.
39. The future is big graphs: a community view on graph processing systems.
40. ARENA: Asynchronous Reconfigurable Accelerator Ring to Enable Data-Centric Parallel Computing.
41. HAM: Hotspot-Aware Manager for Improving Communications With 3D-Stacked Memory.
42. MLIR Loop Optimizations for High-Level Synthesis: A Case Study.
43. SODA-OPT an MLIR based flow for co-design and high-level synthesis.
44. Hardware acceleration of complex machine learning models through modern high-level synthesis.
45. PIMS: a lightweight processing-in-memory accelerator for stencil computations.
46. MAC: Memory Access Coalescer for 3D-Stacked Memory.
47. Advert: An Asynchronous Runtime for Fine-Grained Network Systems.
48. Software defined architectures for data analytics.
49. Scaling and Quality of Modularity Optimization Methods for Graph Clustering.
50. A Parallel Graph Environment for Real-World Data Analytics Workflows.
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