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Memristors as non-volatile memory devices have been recognized for executing in-memory computation in neuromorphic hardware. In this paper, a multilayer neural network has been developed with memristor-bridges as electrical synapses and trained with modified-chip-in-the-loop technique for an image classification task. Modeling the ideal conduction behavior of memristors by their device-physics inspired analytical model has yielded satisfactory performance. However, repeated voltage cycling degrades the resistance window of memristors by aggregating conductive residuals in filamentary memristors. Therefore, emulation of such nonideality has demonstrated compromised results. To improve the performance, refresh pulses have been introduced to the devices in between write pulses to eradicate the fundamental reason of the degradation — i.e., the residuals. It has been observed that improvement of performance is contingent upon the refreshment frequency, and frequent refreshment has the ability to restore performance to a level closely approaching its ideal emulation. [ABSTRACT FROM AUTHOR]

The fourth fundamental circuit element, the memristor, has become a promising candidate to substantially improve the energy and area efficiencies of circuits as traditional complementary metal-oxide-semiconductor (CMOS) technology is approaching its physical limit. However, a mathematical representation of the experimentally obtained current-voltage characteristic of the memristor is necessary to develop and test memristor-based circuitry in electrical design simulators. Here we have developed a behavioral model for the I-V trace of a Pt/TiO2/Pt memristor that can relate the fitting equations with the physical processes associated with the device in response to applied electrical excitation. Multiple conduction mechanisms are involved in memristor that depend upon its latest state. Therefore, the I-V has distinct segments that altogether form a hysteresis loop pinched at the center. In accordance with the predominant conduction mechanisms at each segment, our model defines the form of the equations. The behavioral model can adequately represent the experimental I-V retrieved from existing work. [ABSTRACT FROM AUTHOR]

Wurtzite Zn1−xMgxO nanowires (NWs) are grown using metalorganic chemical vapor deposition technique with the highest Mg mole fraction of 0.29. The physical structure of the NWs remains invariant with increasing Mg incorporation while the diameters and lengths vary in the range 40–180 nm and 0.5–1.5 μm, respectively. Room temperature photoluminescence shows near band edge emission associated with free exciton emission that shifts to shorter wavelength with an increase in the Mg mole fraction. Hall measurement shows that electron mobility decreases with increasing Mg concentration. Revised elastic constants are suggested to explain the observed decrease in the lattice volume at a low Mg mole fraction. [ABSTRACT FROM AUTHOR]

In this work, engineered nanostructures (ENS) have been fabricated on the packed integrated circuits. Coding lookup tables were developed to assign different digits in numerical matrices to different fabricated nano-signatures. The numerical matrices are encrypted according to advanced encryption standard (AES). The encrypted numerical matrix is ink printed on the components, and the nanosignatures are fabricated on the packaged of the chips via electron beam lithography (EBL). This process is to be done in the manufacturer side of the supply chain. The numerical matrix and the nanosignature accompany the product in its long journey in the global supply chain. The global supply chain is proved to be susceptible to counterfeiters. For keeping counterfeiters' hands out of the process, the cipher key and the coding lookup tables are provided to the consumer using a secure direct line between the authentic manufacturer and the consumer. In the consumer side, the printed numerical matrix is decrypted. Having the decrypted numerical matrix makes it possible to extract the nanosignature from the laser speckle pattern shined on the packaged product. In this work, an algorithm is developed to extract the nano-signature by having the decrypted matrix and reflected laser speckle patterns as inputs. Confirming the existence of the nano-signature confirms the authenticity of the component. Imitating the nano-signatures by the counterfeiters is not possible because there is no way for them to observe the shape of these signatures without having access to the cipher key. [ABSTRACT FROM AUTHOR]

In this paper, a novel approach for marking integrated circuit packages with authentication nanosignatures is introduced. In this work, the signatures patterns are fabricated using electron beam lithography. Moreover, the robustness of these signatures against aging and humidity is investigated. A recipe comprising image processing techniques and measurement of similarity indices has been developed. These signatures are proposed to be fabricated at the manufacturer side of the supply chain. Then, they are decoded at the consumer end. Thus, robustness against ambient environment and aging is a requirement for these signatures to survive in the global supply chain. Calculated Mean Square Error and Structural SIMilarity Index confirmed that the reflected patterns of the signatures remain unchanged against aging and humidity. [ABSTRACT FROM AUTHOR]