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32 results on '"Aoudni, Yassine"'

8. Object-oriented approach to Rapid Custom Instruction design

Author

Kallel, Emna, Aoudni, Yassine, and Abid, Mohamed

Subjects
Computer Science - Hardware Architecture
Abstract

Due to continuous evolution of Systems-on-Chip (SoC), the complexity of their design and development has augmented exponentially. To deal with the ever-growing complexity of such embedded systems, we introduce, in this paper, an object-oriented approach to rapid SoC design using auto-generation of hardware custom instructions to simplify and accelerate the SoC design process. In our approach, a Data Flow Graph (DFG) is adopted as a representation of the arithmetic operation to convert it to a custom instruction. Then VHDL code will be automatically generated. The input C code is automatically updated for calling the new hardware components. To prove the effectiveness of the proposed approach, a Java source code framework named Automatic Custom Architecture generator (ACAgen) is developed. Experimental results on 3D sample application validate our approach and demonstrate how the proposed framework facilitates and accelerates the SoC design process at low costs., Comment: IEEE 2012

Published
2013
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9. Mppsocgen: A framework for automatic generation of mppsoc architecture

Author

Kallel, Emna, Aoudni, Yassine, Baklouti, Mouna, and Abid, Mohamed

Subjects
Computer Science - Distributed, Parallel, and Cluster Computing, Computer Science - Hardware Architecture
Abstract

Automatic code generation is a standard method in software engineering since it improves the code consistency and reduces the overall development time. In this context, this paper presents a design flow for automatic VHDL code generation of mppSoC (massively parallel processing System-on-Chip) configuration. Indeed, depending on the application requirements, a framework of Netbeans Platform Software Tool named MppSoCGEN was developed in order to accelerate the design process of complex mppSoC. Starting from an architecture parameters design, VHDL code will be automatically generated using parsing method. Configuration rules are proposed to have a correct and valid VHDL syntax configuration. Finally, an automatic generation of Processor Elements and network topologies models of mppSoC architecture will be done for Stratix II device family. Our framework improves its flexibility on Netbeans 5.5 version and centrino duo Core 2GHz with 22 Kbytes and 3 seconds average runtime. Experimental results for reduction algorithm validate our MppSoCGEN design flow and demonstrate the efficiency of generated architectures., Comment: 16 pages; International Journal of Computer Science & Information Technology (IJCSIT) Vol 4, No 2, April 2012

Published
2012
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10. VANET Network Traffic Anomaly Detection Using GRU-Based Deep Learning Model

Author

ALMahadin, Ghayth, Aoudni, Yassine, Shabaz, Mohammad, Agrawal, Anurag Vijay, Yasmin, Ghazaala, Alomari, Esraa Saleh, Al-Khafaji, Hamza Mohammed Ridha, Dansana, Debabrata, and Maaliw, Renato Racelis

Abstract

The rise of Vehicular Ad-hoc Networks (VANETs) has led to the growing significance in intelligent transportation systems. This research suggests a deep learning model for anomaly detection based on GRU over VANET network traffic to address this challenge. Consumer electronics technologies can be successfully introduced to the market in one of two ways: either there is a clear benefit for the customer from using this technology, or it is required by a regulatory order that prevents the use of alternatives. It is possible to detect unknown assaults and DoS floods using traffic anomalies. Users can keep track of the security features of multimedia services by using Traffic Anomaly Detection, which provides an overview of traffic anomaly detection analysis. Anomaly detection methods fall into three categories: unsupervised, semi-supervised, and supervised. The right anomaly detection technique basically depends on the labels that are present in the dataset. To further improve the accuracy of proposed model, a new semi-supervised technique for detecting VANET network activity anomalies called SEMI-GRU has been proposed. The results demonstrate that proposed GRU-based deep learning model outperforms existing methods in detecting network anomalies with low false positive rates.

Published
2024
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19. EXPLOITING PARTIALLY RECONFIGURABLE FPGA FOR PERFORMANCE ADJUSTMENT IN THE RVC FRAMEWORK

Author

Hentati, Manel, Aoudni, Yassine, Nezan, Jean François, Abid, Mohamed, Département de Génie Électrique de Sfax [ENIS] (CEM Lab - ENIS), École Nationale d'Ingénieurs de Sfax | National School of Engineers of Sfax (ENIS), Institut d'Électronique et des Technologies du numéRique (IETR), Université de Nantes (UN)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), Université européenne de Bretagne - European University of Brittany (UEB), Nantes Université (NU)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), and Université de Nantes (UN)-Université de Rennes 1 (UR1)

Subjects
Dynamic Partial Reconfiguration, Computer Science::Hardware Architecture, [INFO.INFO-MM]Computer Science [cs]/Multimedia [cs.MM], Hadamard transform, FPGA, RVC framework, [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract

International audience; In this paper, we present a method to implement a specific algorithm using the RVC framework and the dynamic partial reconfiguration (DPR). The DPR is a technique allowing to replace modules in a design at run-time. While, the RVC framework is based on the use a specific language for writing dataflow models called RVC-CAL. The studied algorithm is a Hadamard transform. Several dataflow models of the Hadamard transform can be used in the design process in order to favor speed or power consumption. We show the steps required to implement and switch between two dataflow models (a sequential model and a pipelined model) of the Hadamard transform. Our design allows to user to choose one of two architectures according her requirements of low power and high speed.

Published
2012

20. A HIERARCHICAL IMPLEMENTATION OF HADAMARD TRANSFORM USING RVC-CAL DATAFLOW PROGRAMMING AND DYNAMIC PARTIAL RECONFIGURATION

Author

Hentati, Manel, Aoudni, Yassine, Nezan, Jean François, Abid, Mohamed, Département de Génie Électrique de Sfax [ENIS] (CEM Lab - ENIS), École Nationale d'Ingénieurs de Sfax | National School of Engineers of Sfax (ENIS), Institut d'Électronique et des Technologies du numéRique (IETR), Nantes Université (NU)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), Université européenne de Bretagne - European University of Brittany (UEB), Université de Nantes (UN)-Université de Rennes 1 (UR1), Université de Nantes (UN)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), and Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)

Subjects
[INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [INFO.INFO-MM]Computer Science [cs]/Multimedia [cs.MM], [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract

International audience; This paper presents an efficient design method used to implement a hierarchical architecture of Hadamard transform module. The proposed design method is based on the use of RVCCAL dataflow approach and dynamic partial reconfiguration technique (DPR). The DPR technique allows reconfiguring a part of the FPGA area with different functionalities at runtime. It is a promising solution to increase performance in the system. RVC-CAL is a specific language for writing dataflow models which is introduced by MPEG-RVC video standard. RVC-CAL description is composed of a set of interconnected blocks (actors). Several dataflow models of the same application can be used in the design process. In this work, the hierarchical architecture of Hadamard module is composed of three levels. And each one contains a set of blocks. The DPR is applied between these blocks to switch from level to another. To achieve this implementation, in the first, the Hadamard blocks are described in RVC-CAL language and a specific RVC-CAL tool is used to generate automatically their hardware description. Then, the DPR design flow is applied. In our design method, we use xilinx tools and Virtex-5 FPGA board. To evaluate our implementation, we compare its with two other architectures in terms of area occupation, power consumption and execution time.

Published
2012

23. Sustainable electric vehicles fault detection based on monitoring by deep LearningArchitectures in feature extraction and classification

Author

Wongchai, Anupong, Aoudni, Yassine, Yesubabu, Mannava, Ahmad Reegu, Faheem, Vasantha Gowri, N., and Vijayakumar, P.

Abstract

•This research proposes novel technique in electric vehicle fault detection based on monitoring data classification and feature extraction using deep learning architectures.•Here the input data has been collected as sustainable electric vehicles data using multi-cell parallel electric vehicle and this data has been processed for noise removal and dimensionality reduction.•The processed data features have been extracted using deep stacking auto gradient descent.•Then the extracted features have been classified using monte carlo regressive Gaussian naïve bayes architecture.

Published
2023
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30. Automatic generation of Coprocessor program from VHDL description.

Author

Kallel, Emna, Aoudni, Yassine, and Abid, Mohamed

Abstract

The design and implementation of complex embedded systems including custom hardware and software is still to a large degree based on a collaboration of semi-manual and often poorly interconnected design methods and tools. This usually results in repetitive and longer development cycles. This paper describes an intelligent method to automate and accelerate the hardware generation process. Indeed, a VHDL parser is developed to provide an automated path from VHDL entry to Coprocessor design. To prove the correctness of our method, a Java source code framework named Automatic Custom Architecture generator (ACAgen) is developed. Experimental results on 3D sample application show that the proposed framework can rapidly and easily generate coprocessor. It leads to the design of large and complex systems-on-chip with less costs and higher performances. [ABSTRACT FROM PUBLISHER]

Published
2012

32. A FRAMEWORK FOR ASIPAND MULTIPROCESSOR ARCHITECTURES INTEGRATION WITHIN RECONFIGURABLE SOC AND FPGADEVICES.

Author

Aoudni, Yassine, Abid, Mohamed, Gogniat, Guy, and Philippe, Jean-Luc

Subjects
*MULTIPROCESSORS, *INFORMATION technology, *COMPUTER input-output equipment, *COMPUTER software, *ELECTRONIC circuits, *INTEGRATED circuits
Abstract

Application-Specific Instruction-set Processors (ASIPs) have gained popularity in production chips as well as in the research community. They offer a viable solution to the tradeoff between efficiency and flexibility for the embedded System-on-a- Chip (SoC). Generally, an ASIP has the capability to extend the base instruction set of a general-purpose processor with a set of customized instructions supported by the specific hardware resources provided on the ASIP. The hardware implementing the specific instructions can be either runtime reconfigurable functional units, or pre-synthesized circuits. In this paper, we propose a framework for prototype application within FPGAs devices using ASIPs and multiprocessors architecture. Firstly, we provide an overview of a method to identify coarse and finite grain instruction set extensions in application code and integration process of ASIP. Second, we split the data input application to get concurrence and the data dependency of the target application in order to process to multiprocessor execution. Finally, we compare the performances levels given by the execution of the application using ASIP architecture and multiprocessor architecture. [ABSTRACT FROM AUTHOR]

Published
2007

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