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Approximate computing (AC) in arithmetic logic has become a viable option in applications requiring error tolerance in energy-efficient architectures. AC relied on approximate arithmetic functions to reduce delay, area, and power consumption while sacrificing accuracy to reduce delay, power, and area. In this research, a novel two approximate recursive multipliers (RMul-1, RMul-2) and an approximate adder have been designed to reduce power consumption, area, and computational delay in error-tolerant systems. The recursive multipliers utilize a combination of NOR, AND, half adder, and full adder gates to achieve low power and area-efficient designs. Furthermore, to reduce time, the approximation adder uses an optimal combination of AND, OR, and MUX gates. Furthermore, the cadence RTL compiler synthesizes the proposed multiplier using 28nm technology, and it is compared to previous approximation multipliers. Image processing applications are simulated, and the performance of the proposed multipliers is verified using simulations using the Xilinx ISE 13.2 tool. The proposed RMul designs outperform current techniques by up to 30.3% in area, 20.2% in power, and 43.9% in delay, according to experimental results. In addition, the suggested multipliers outperform existing multipliers in terms of SSIM and PSNR. [ABSTRACT FROM AUTHOR]

Artificial neural networks have been one of the science’s most influential and essential branches in the past decades. Neural networks have found applications in various fields including medical and pharmaceutical services, voice and speech recognition, computer vision, natural language processing, and video and image processing. Neural networks have many layers and consume much energy. Approximate computing is a promising way to reduce energy consumption in applications that can tolerate a degree of accuracy reduction. This paper proposes an effective method to prevent accuracy reduction after using approximate computing methods in the CNNs. The method exploits the k-means clustering algorithm to label pixels in the first convolutional layer. Then, using one of the existing pruning methods, different pruning amounts have been applied to all layers. The experimental results on three CNNs and four different datasets show that the accuracy of the proposed method has significantly improved (by 17%) compared to the baseline network. [ABSTRACT FROM AUTHOR]

In the nano-scale era, enhancing speed while minimizing power consumption and area is a key objective in integrated circuits. This demand has motivated the development of approximate computing, particularly useful in error-tolerant applications such as multimedia, machine learning, signal processing, and scientific computing. In this research, we present a novel method to create approximate integer multiplier circuits. This work is based on a modification of the well-known Wallace tree multiplier, called the Reduced Complexity Wallace Multiplier (RCWM). Approximation is introduced by replacing conventional Full Adders with approximate ones during the partial product reduction phase. This research investigates the characteristics of 8×8-, 16×16-, and 32×32-bit Approximate Reduced Complexity Wallace Multipliers (ARCWM), evaluating their accuracy, area usage, delay, and power consumption. Given the vast search space created by different combinations and placements of these approximate Adders, a Genetic Algorithm was used to efficiently explore this space and optimize the ARCWMs. The resulting ARCWMs have an area reduction of up to 65% and a power consumption reduction of up to 70%, with no worse delay than the RCWM. Multipliers created with this method can be used in any application that requires parallel multiplication, such as neural accelerators, trading accuracy for area and power reduction. Additionally, an ARCWM can be used alongside a slow shift-and-accumulate multiplier trading off accuracy for faster calculation. This methodology provides valuable guidance for designers in selecting the optimal configuration of approximate Full Adders, tailored to the specific requirements of their applications. Alongside the methodology, we provide all of the tools used to achieve our results as open-source code, including the Register-Transfer Level (RTL) code of the 8×8-, 16×16-, and 32×32-bit Wallace Multipliers. [ABSTRACT FROM AUTHOR]

The present era has witnessed the wide deployment of reconfigurable hardware or Field Programmable Gate Arrays (FPGAs) in edge and cloud platforms. With its ability of dynamic partial reconfiguration at runtime, FPGAs provide the apt environment to execute a variety of real-time tasks in strict power and timing constraints. However, threats associated with the vulnerability of hardware like hardware Trojan horses may cause sudden delays at runtime or may even drain the power budget of the system to prevent completion of the tasks before their associated deadlines. We consider a resource-constraint FPGA-based edge platform with strict power budget. This is associated with execution of several periodic and nonperiodic hard real-time approximate computing tasks, i.e., tasks whose result can vary within a certain range but must complete within a prespecified deadline. We depict how delay inducing and power draining hardware Trojans may jeopardize the scenario. We propose deployment of low overhead agents or self-aware modules (SAMs) that can facilitate decentralized control and nonintrusive security in such an environment. With each FPGA that is entrusted with execution of a series of tasks or a task schedule, a SAM is associated. The SAM continuously monitors the performance of its host, based on prespecified power and timing data. On detecting any anomaly, it outsources the tasks to other SAMs for execution in other FPGAs, so that the tasks can complete their execution prior to their deadline. Low resource utilization and timing overhead of SAM, high task success rate for periodic tasks and low task rejection rate for nonperiodic tasks depict the suitability of our proposed mechanism. [ABSTRACT FROM AUTHOR]

Approximate Computing (AC) have widely adopted in designing large-scale logic circuits. In particular, approximate adder and multiplier circuits have been considerably targeted in the realm of image processing due to their high energy-saving while preserving proper level of computing accuracy. Nevertheless, intensive research and development are maintained in the means of seeking more matured designs that effectively prioritize design overheads over error resilience. In this paper, low error-distance approximate 4:2 compressor circuits are proposed to construct high-speed approximate adders. The developed compressors realize high logic computing and incur competitive area and power consumption, and therefore, they were leveraged to configure an approximate 8×8 multiplier designs. To achieve a favorable trade-off between computational accuracy and hardware resource usage, we develop a simulation framework that evaluates the accuracy of the proposed multiplier designs at the gate-level (measuring error distance) and at the application-level (evaluating SNR and SSIM) of an image. The framework truncates specific propagated carry bits, i.e., least significant bits (LSBs), to realize profitable area- and power-saving. Furthermore, two main high-speed multiplier designs are proposed herein, namely High Computing Performance Approximate Multiplier (HCP-AMUL) and HCP Low Error Approximate Multiplier (HCPLE-AMUL). Matlab R2022b along with VS Code are used for running simulations and accuracy evaluation, while Vivado 2018.2 is utilized for HDL reconfigurable logic design and implementation and evaluation of area, power, and speed, configured on an FPGA Xilinx Nexys 4 Artix-7 (XC7A100T1CSG324) trainer board. The experimental results demonstrate the efficacy of the developed multipliers as the developed HCPLE-AMUL delivers 54.26%, 11.72%, and 449.85 of speedup, power saving, and Power-Delay-AreaError-Product (PDAEP) improvement, respectively. On the other hand, the presented HCP-AMUL realizes an improved saving of area and power at the expense of an acceptable lowering of computation accuracy. It achieves 9.66%, 505.40, and 53.73% of power saving, PDAEP, and speedup respectively, Thus, the proposed compressor and multiplier circuits potentially can be promising approximate computing modules for image processing applications to provide improved trade-off between computation accuracy and logic utilization complexity. [ABSTRACT FROM AUTHOR]

Arithmetic circuits such as adders are fundamental components in implementing image processing applications. Since these applications are error-tolerant, the adders can be approximated to improve their PDP (Power-Delay-Product) metric while maintaining accuracy within tolerance limits. This paper proposes a segmentation technique to design ternary approximate adders, where the entire adder chain is split into segments, with the intent to reduce the delay. Next, for applications that require tunable accuracy, we incorporate a reconfiguration technique in the segmented approximate adders, using a divide-and-conquer methodology that dynamically optimizes the approximate adder’s accuracy, leading to efficient computation. Also, an algorithm was proposed to compute accuracy and hardware complexity in an N-trit accuracy reconfigurable adder. The proposed methodology was validated using an approximate 6-trit adder on its power consumption and delay performance metrics. Compared with the best design in literature, the proposed approximate 6-trit adder exhibits 63% lesser power consumption and 69% lesser delay. The proposed approximate 6-trit adder accuracy was progressively enhanced through the reconfigurable method. After a few reconfiguration stages, the proposed adder matched the accuracy of an exact 6-trit adder while achieving an improved power-delay product (PDP). Finally, the proposed 6-trit adders were validated by using them in the image-blending application.

Implementation of Convolutional Neural Networks (CNNs) on edge devices require reduction in computational complexity. Leveraging optimization techniques or approximate computing techniques can reduce the overhead associated with hardware implementation. In this paper, we propose a modular pipelined Feedforward CNN Hardware Accelerator (FHA) and a novel Approximate Feedforward CNN Hardware Accelerator (AFHA). The AFHA design is achieved through the incorporation of hardware pruning and Approximate Multiply Accumulate (AMAC) units. Our proposed architectures are validated for functionality through an image classification application, utilising the popular MNIST dataset for 8-bit, 16-bit and 32-bit operational word size. Performance analysis of our proposed architectures show that the 32-bit FHA consumes 307.04pJ of energy while achieving acceleration of 76.91x. AFHA attains an acceleration of 120.69x with an energy consumption of 295.85pJ. Similarly, the 16-bit and 8-bit architectures demonstrate substantial acceleration while significantly reducing power consumption. The performance of our proposed architectures demonstrates significant acceleration and reduced power consumption compared to popular edge machine learning framework - TinyML TensorFlow Lite. FHA achieves a significant accuracy improvement of 6.2% along with a speedup of 1.07x and AFHA achieves accuracy enhancement of 4.3% and an impressive speedup of 1.42x.

Media processing applications can tolerate error up to a certain limit due to the perceptual limitations of the human eye. Since adders are ubiquitous in power-hungry media processing applications, they can be approximated without much compromise in quality. An adder with better error characteristics without significant compromise in area and power is required to meet the future demands of ever-increasing computational needs. In order to achieve the same, a novel segmentation technique has been proposed. By varying the number of bits in each segment, three different designs are proposed, each with its advantage. Each proposed adder is segmented into three portions, namely Most Significant Portion (MSP), Intermediate Significant Portion (ISP) and Least Significant Portion (LSP). The sub-adder's sum in each portion is computed concurrently to reduce the critical path delay. The proposed heterogeneous adder (HEAD) designs achieve better accuracy than the state-of-the-art designs. Synthesis results show that HEAD consumes less area up to 41.8% and consumes less power ranging from 0.8% to 51%, than existing adders. Exhaustive simulations are carried out on benchmarking image sharpening application to prove that the proposed adders obtain a better quality-effort tradeoff than the existing designs. [ABSTRACT FROM AUTHOR]

Multiple signal classification (MUSIC) is a widely used direction of arrival (DoA)/angle of arrival (AoA) estimation algorithm applied to various application domains, such as autonomous driving, medical imaging, and astronomy. However, MUSIC is computationally expensive and challenging to implement in low-power hardware, requiring exploration of tradeoffs between accuracy, cost, and power. We present MUSIC-lite, which exploits approximate computing to generate a design space exploring accuracy-area-power tradeoffs. This is specifically applied to the computationally intensive singular value decomposition (SVD) component of the MUSIC algorithm in an orthogonal frequency-division multiplexing (OFDM) radar use case. MUSIC-lite incorporates approximate adders into the iterative CORDIC algorithm that is used for hardware implementation of MUSIC, generating interesting accuracy-area-power tradeoffs. Our experiments demonstrate MUSIC-lite’s ability to save an average of 17.25% on-chip area and 19.4% power with a minimal 0.14% error for efficient MUSIC implementations. [ABSTRACT FROM AUTHOR]

In this paper, a multichannel FIR filter design based on the Time Division Multiplex (TDM) approach that incorporates one multiply and add unit, regardless of the variable coefficient length and varying channels, by associating the resource sharing doctrine is suggested. A multiplier based on approximate distributed arithmetic (DA) circuits is employed for effective resource optimization. Although no explicit multiplication was conducted in this realization, the radix-8 and radix-4 Booth algorithms are utilized in the DA framework to curtail and optimize the partial products (PPs). Furthermore, the input stream is truncated with an erratum mending unit to roughly construct the partial products. For an aggregation of PPs, an approximate Wallace tree is taken into consideration to further minimize hardware expenses. Consequently, the suggested design's latency, utilized area, and power usage are largely reduced. The Xilinx Vertex device is expedited, given the synthesis of the suggested multichannel realization with 16 taps, which is simulated using the Verilog formulary. It is observed that the filter structure with one channel produced the desired results, and the system's frequency can support up to 429 MHz with a reduced area. Utilizing TSMC 180 nm CMOS technology and the Cadence RC compiler, cell-level performance is also achieved. [ABSTRACT FROM AUTHOR]

The energy-efficient error-tolerant circuits have paved the way for a whole new area in low-power consumption applications with approximate computing. The approximate computing fulfills the trade-off requirement of exact computation and provides efficient performance. In this paper, a novel energy-efficient multiplier has been proposed for image processing applications. In the multiplication process, compressors are used as an important component for the reduction of partial products. Higher-order approximate 5:2 and 6:2 compressors are also designed and simulated in VIVADO using Verilog coding. The proposed higher-order compressors result in less area and low-power consumption in comparison with the existing state-of-the-art technique. These high-performance compressors are used at the multipliers’ reduction stage, resulting in an energy-efficient circuit for error-tolerant applications. All the simulations were carried out in VIVADO considering 8-bit inputs. Multiplication performance shows 37.77 % (8-bit) improvement in terms of power consumption in comparison to the conventional multiplier. The multiplication process has been done on the original, negative, and sharpened images using their masks. The proposed multiplier shows 51.36% (original image), 6.04% (negative image), and 22.44% (sharpened image) PSNR improvement in comparison to state-of-the-art work. [ABSTRACT FROM AUTHOR]

Approximate computing enables high performance and efficiency of execution by using the overhead on compute units of a processor to give high speed. The speed and system delay are inversely proportional, necessitating massive parallel processes with massive hardware and power dissipation. Energy and area-efficient systems can be realized by reducing system accuracy and dependability. Approximate computing techniques can be used to reduce the number of computing resources needed for a given task and improve the performance of a system. This can be accomplished by lowering a computational model's accuracy and decreasing complexity, reducing power consumption, latency, and area requirements. This study examines an electrical circuit that performs multiplication of two equal integers and it proposes the use of a carry-in adder with two approximation compressors to reduce the size, latency, and power consumption while maintaining the same level of accuracy as current designs. The suggested algorithms were implemented in Xilinx Vivado and their effectiveness was evaluated using numerical performance metrics, including error rate, power consumption, delay, and power delay product in output result. The compressors suggested are used to implement 8 × 8 and 16 × 16 Dadda multipliers that perform comparably to state-of-the-art approximation multipliers. [ABSTRACT FROM AUTHOR]

Approximate computing plays a crucial role in faster operation for large-scale data computation in error-resilient applications. An approximate adder is a digital circuit that performs addition with less accuracy to achieve faster processing time and lower hardware overhead. This approach is well suited for error-tolerant applications where minor errors in the output are acceptable. In this paper, an approximate carry prediction adder (ACPA) is proposed to add the mantissa in a 32-bit single precision floating point adder, termed as approximate floating point precise carry prediction adder (AFPCPA). The proposed ACPA utilizes a carry prediction circuit to generate a precise carry for the precise part leading to an increase in accuracy. The error characteristics and hardware utilization of AFPCPA and other existing approximate adder architectures are compared. The results show that the proposed AFPCPA vide, on average, 50.56%, 59.66%, 56.13%, and 81.40% reduction in standard deviation, mean absolute error, normalized mean error distance, and mean square error, respectively. In addition, the proposed AFPCPA shows on average, 18.97% and 6.68% lesser hardware utilization and delay, respectively compared to existing approximate adder architectures and accurate adder. Finally, a 3-tap FIR Filter is designed using the proposed AFPCPA and compared with existing architectures. [ABSTRACT FROM AUTHOR]

Approximate computing is a technique for optimising algorithms while taking into account both application quality of service and computational complexity. Video encoding is a computationally difficult operation, and the complexity is growing as new compression standards, such as Versatile Video Coding (VVC), emerge. Because it uses several new coding methods, the VVC standard delivers superior video compression. However, the human perceptual constraint presents a good chance for a new alternative form of computation, such as approximation computing, which allows for some acceptable level of inaccuracy in the output. In this paper, first, the VVC coding tools are analysed to determine the most computationally complex functions of various coding tools as the best candidates to perform approximate computing. Because addition is a frequent operation employed in all reletaed functions of various coding tools and no one would be feasible without an efficient adder circuit, correct approximate computing is done to the adder circuits of these chosen candidate functions. First, the LOA approximation adder is employed, which achieves 9.67x and 5x power and area reductions, respectively, as compared to the original VVC as the baseline, with no discernible influence on subjective quality. The AxMAP framework is then examined to build more effective approximate adders, which lowered the area and power consumption by 14.88% and 9.11%, respectively, over the LOA technique. [ABSTRACT FROM AUTHOR]

The escalating computational demands of deep learning and large-scale models have led to a significant increase in energy consumption, highlighting the urgent need for more energy-efficient hardware designs. This study presents a novel weight approximation strategy specifically designed for quantized neural networks (NNs), resulting in the development of an efficient approximate multiplier leveraging most significant one (MSO) shifting. Compared to both energy-efficient logarithmic approximate multipliers and accuracy-prioritized non-logarithmic approximate multipliers, our proposed logarithmic-like design achieves an unparalleled balance between accuracy and hardware costs. When compared with the baseline exact multiplier, our innovative design exhibits remarkable reductions, encompassing a decrease of up to 28.31% in area, a notable 57.84% reduction in power consumption, and a diminution of 11.86% in delay. Experimental outcomes reveal that the proposed multiplier, when applied in neural networks, can conserve approximately 60% of energy without compromising task accuracy. Concurrently, experiments focused on the transformer accelerator and image processing illustrate the substantial energy savings that can be obtained for Large Language Models (LLMs) and image processing tasks through the implementation of our proposed design, further validating its efficacy and practicality. [ABSTRACT FROM AUTHOR]

Vector normalization is an important process in several algorithms. It is used in classical physical calculations, mathematical techniques, and machine learning, which has witnessed significant advancements in recent years. Normalization and regularization ensure the stability of solutions and play an important role in algorithm convergence. Normalization typically refers to the division of elements by their norm. Division should not be used in algorithmic implementations because its computational cost is considerably higher than that of multiply–add operations. Based on this, there is a well-known method referred to as the fast inverse square root (FISR) algorithm in floating-point calculations (IEEE754). In deeper-level embedded systems that require fast responses or power efficiency, integer instead of real number arithmetic (floating-point number arithmetic) should be used to increase speed. Conversely, in deeper-level embedded systems that require fast responses or power efficiency, integer arithmetic should be used instead of real number arithmetic (floating-point number arithmetic) to increase speed. Therefore, embedded engineers encounter problems in instances in which they use integer arithmetic for implementation, but real number arithmetic is required to compute vectors and other higher-dimensional algebra. There is no conventional normalization algorithm similar to the FISR algorithm for integer arithmetic; however, the proposed pseudo-normalization achieves vector normalization within a restricted domain using only multiply–add operations and bit shifts. This allows for fast and robust operations, even for low-performance MCUs that do not have power-efficient FPUs. As an example, this study demonstrates the computation of the arctangent (Arctan2 function; atan2(y, x)) with high precision using only integer multiply–add operations. In this study, we proposed a method of vector normalization using only integer arithmetic for embedded systems and confirmed its effectiveness by simulation using Verilog. The research results can contribute to various fields such as signal processing of IMU sensor data, faster artificial intelligence training, and efficient rendering of computer graphics. [ABSTRACT FROM AUTHOR]

In artificial intelligence, the large role is played by machine learning (ML) in a variety of applications. This article aims at providing a comprehensive survey on summarizing recent trends and advances in hardware accelerator design for machine learning based on various hardware platforms like ASIC, FPGA and GPU. In this article, we look at different architectures that allow NN executions in respect of computational units, network topologies, dataflow optimization and accelerators based on new technologies. The important features of the various strategies for enhancing acceleration performance are highlighted. The numerous current difficulties like fair comparison, as well as potential subjects and obstacles in this field has been examined. This study intends to provide readers with a fast overview of neural network compression and acceleration, a clear evaluation of different methods, and the confidence to get started in the right path. [ABSTRACT FROM AUTHOR]

Bilateral filtering is an image processing technique commonly adopted as intermediate step of several computer vision tasks. Opposite to the conventional image filtering, which is based on convolving the input pixels with a static kernel, the bilateral filtering computes its weights on the fly according to the current pixel values and some tuning parameters. Such additional elaborations involve nonlinear weighted averaging operations, which make difficult the deployment of bilateral filtering within existing vision technologies based on real-time and low-energy hardware architectures. This paper presents a new approximation strategy that aims to improve the energy efficiency of circuits implementing the bilateral filtering function, while preserving their real-time performances and elaboration accuracy. In contrast to the state-of-the-art, the proposed technique allows the filtering action to be on the fly adapted to both the current pixel values and to the tuning parameters, thus avoiding any architectural modification or tables update. When hardware implemented within the Xilinx Zynq XC7Z020 FPGA device, a 5 × 5 filter based on the proposed method processes 237.6 Mega pixels per second and consumes just 0.92 nJ per pixel, thus improving the energy efficiency by up to 2.8 times over the competitors. The impact of the proposed approximation on three different imaging applications has been also evaluated. Experiments demonstrate reasonable accuracy penalties over the accurate counterparts. [ABSTRACT FROM AUTHOR]

AI systems have an increasing sprawling impact in many application areas. Embedded systems built on AI have strong conflictual implementation constraints, including high computation speed, low power consumption, high energy efficiency, strong robustness and low cost. Neural Networks (NNs) used by these systems are intrinsically partially tolerant to computation disturbances. As a consequence, they are an interesting target for approximate computing seeking reduced resources, lower power consumption and faster computation. Also, the large number of computations required by a single inference makes hardware acceleration almost unavoidable to globally meet the design constraints. The reported study, based on an integer version of LeNet, shows the possible gains when coupling approximation and hardware acceleration. The main conclusions can be leveraged when considering other types of NNs. The first one is that several approximation types that look very similar can exhibit very different trade-offs between accuracy loss and hardware optimizations, so the selected approximation has to be carefully chosen. Also, a strong approximation leading to the best hardware can also lead to the best accuracy. This is the case here when selecting the ApxFA5 adder approximation defined in the literature. Finally, combining hardware acceleration and approximate operators in a coherent manner also increases the global gains. [ABSTRACT FROM AUTHOR]

As cloud computing continues to evolve, the demand for scalable and energy-efficient infrastructure to handle extensive applications becomes paramount. Traditional transistor scaling and microprocessor design methods no longer suffice to meet the growing scale of cloud usage. This research explores the potential of approximate computing (AC) as an innovative solution to these challenges, particularly in high-demand computational settings. AC, known for its ability to make controlled accuracy trade-offs, is identified as a key strategy for improving both the performance and energy efficiency of cloud infrastructure, with a focus on low-power Field-Programmable Gate Array (FPGA) designs. This paper introduces novel methodologies that harness the strengths of AC, emphasizing its application in neural-based and machine-learning techniques for energy-efficient solutions. By targeting the performance of AC, especially in varied application domains and complex data mining scenarios, we propose two groundbreaking approaches that significantly enhance computational speed and reduce energy consumption. Our empirical analysis demonstrates notable improvements over existing techniques, highlighting the effectiveness of AC in optimizing cloud infrastructure. The proposed model on FPGA through cloud computing attains substantial elevation rates by 89 % and energy reduction by 122 %, which had been good outcomes. This study not only confirms the benefits of integrating AC with low-power FPGA designs for cloud environments but also sets a new benchmark for future research in achieving more sustainable and efficient cloud computing via VLSI FGPA design analysis solutions. [ABSTRACT FROM AUTHOR]