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We propose, for the first time, an indium gallium zinc oxide (IGZO)-based 2T1C compute cell (IGZO-cell) for analog in-memory computing. To assess the impact of an IGZO-cell-based array including the periphery on power and accuracy, a PyTorch framework was developed to analytically modeled analog components. The results are reported for a ResNet20 network on the Canadian Institute For Advanced Research-10 (CIFAR-10) benchmark. The state-of-the-art energy efficiency of 15 peta operations per second (POPS)/W including the periphery is achieved by using our proposed IGZO-cell with CMOS compatibility. Finally, it is shown that, with a properly trained neural network model, there is no degradation of test accuracy with 10% device to device variability for the IGZO devices.

BACKGROUND The most dramatic feature of modern obstetrics is the relentless increase in the caesarean section rate. WHO suggests a caesarean rate of above 15% is unnecessary and unjustified. WHO reviewed and said that most women who need caesarean section should receive it. This escalating caesarean section rate is a major public health problem because it increases the health risk for mothers and babies as well as the cost of health care when compared with normal deliveries. We wanted to determine the demographic and etiological factors which lead to the rising trends of caesarean section in a tertiary center. METHODS It’s a cross sectional observational study among all the subjects undergoing caesarean section in the period of January, 2018 to December 2018, in Agartala Govt. Medical College, in the department of obstetrics and gynaecology. Information regarding socio demographic factors, indication of caesarean section, maternal and neonatal outcome was recorded in pre-designed pretested questionnaire. RESULTS In this study, the commonest indication found for caesarean section is previous caesarean section (68.8%). Most of the subjects were primigravida (43.1%); commonest age group was

Analog in memory computing (AiMC) is a promising hardware solution to efficiently perform inference with deep neural networks (DNNs). Similar to digital DNN accelerators, AiMC systems benefit from aggressively quantized DNNs. In addition, AiMC systems also suffer from noise on activations and weights. Training strategies to condition DNNs against weight noise can increase the efficiency of AiMC systems by enabling the use of more compact but more noisy weight memory devices. In this work, we utilize noise-aware training and introduce gradual noise training and network width scaling to increase the tolerance of DNNs against weight noise. Our results show that noise-aware training and gradual noise training drastically lowers the impact of weight noise without changing the network size. By utilizing network width scaling, the weight noise tolerance is increased even more with the penalty of more network parameters.

This paper describes the design of two A/D converters, the Charge Sharing SAR and the Charge Injection SAR, in 22 nm FD SOI technology, for Analog-in-Memory computing in machine learning (ML) applications. The former architecture matches well SRAM-based Matrix-Vector Multipliers (MVM)s, whereas the latter is suitable for integration with SOT-MRAM-based arrays. Both ADCs show remarkable energy figures and area metrics, making the topologies suitable for integration at the periphery of MVM arrays.

Deep neural network (DNN) inference for edge AI requires low-power operation, which can be achieved by implementing massively parallel matrix-vector multiplications (MVM) in the analog domain on a highly resistive memory array. We propose a 1T1R compute cell (1T1R-cell) using a ferroelectric hafnium oxide-based FET (FeFET) and TiN/SiO 2 tunneling junction of MΩ resistor (MOR) for analog in-memory computing (AiMC). The MOR exhibited a tunneling current behavior and MΩ resistance. A 1T1R-cell array-level evaluation was also performed. A random access for writing with low write disturbance scheme was confirmed from the summation-DC-current output, and binaries were successfully classified into “T” and “L.” Based on the experimental results of our proposed 1T1R-cell, we obtained a state-of-the-art energy efficiency of 13700 TOPS/W including the periphery. Furthermore, we confirmed that a high inference accuracy can be obtained with our low-resistance-variability 1T1R-cell with a properly trained model.

Deep learning constitutes the state-of-the-art in machine learning, from data mining to computer vision and natural language processing. Energy-efficient matrix-vector multiplications (MVMs) [1] are key to bringing these capabilities to the edge, for both convolutional and recurrent neural networks. Since low precision multiplications with a limited level of noise can achieve relatively high accuracies [2], a compelling opportunity arises for mixed-signal hardware implementations to exploit in-memory computing paradigms [3– 6]. In this work, a matrix-vector multiplier is presented operating on ternary weights, 7-bit input (6-bit magnitude and 1-bit sign), and 6-bit output activations. Notable improvements in energy efficiency and peak compute throughput per unit area are exhibited by measurements on a test chip based on the GLOBALFOUNDRIES® 22FDX® FD-SOI platform, thanks to a novel SRAM-based compute cell with low “on” current, pulse-width encoded input activations, a clamp-free summation line, and efficient amortization of the ADC and DAC energies.

Puerperium is the time following delivery during which pregnancy-induced maternal anatomical and physiological changes return to the nonpregnant state. Puerperium period of 6 weeks can be divided into: (a) immediate – within 24 hours (b) early – up to 7 days (c) remote – up to 6 weeks. The puerperal effects are seen in all organs and particularly in reproductive organs. Infection and haemorrhage are the common postpartum complications. Post partum care is very important. Advice on exclusive breast feeding and contraception is also mandatory after every childbirth.

Driven by concerns on climate change, resources depletion, local and global pollution, sustainability is becoming an integral component of business and of regulations. The progress of Design Technology Co- Optimization (DTCO) methodologies and tools, building transversal knowledge from manufacturing to design, provides an opportunity to develop a framework for early sustainability assessments of logic technologies. Environmental scores can be derived together with the established Power, Performance, Area, Cost (PPAC) metrics. To demonstrate this approach, we evaluate the energy and water consumption as well as the greenhouse gas emissions trends from processing logic nodes from iN28 to iN3 with different scaling scenarios.

This paper assesses the benefits and pitfalls of Analog in-Memory Compute (AiMC) solutions from the accelerator level. The study shows that AiMC can improve efficiency significantly, yet only when the AiMC array topology and the memory technology are co-optimized with the memory and system architecture. The paper provides design guidelines to maximally exploit the opportunities of AiMC technology, and gives an outlook towards emerging memory technologies.

The global air traffic touched a whopping 3.8 billion in 2016 (IATA 2017), forecasted to grow at a CAGR (Compounded Annual Growth Rate) of 3.7% annually by 2035, with India displaying the highest growth rate of 23%, beating China and US who retained the second and third position respectively. IATA (International Air Transport Association) forecasted the flown passengers to be nearly double at 7.2 billion by 2035 and the top driver of this demand would be the developing economies of the Asia-Pacific region. The expected growth in air traffic is bound to put commendable pressure on airports’ infrastructure, which is already approaching bottlenecks. ACI benchmarked the top twenty airports listed on stock exchange in Asia-Pacific, Europe and United States, according to their passenger volumes in 2016, among which eight were situated in Asia. Considering ACI’s benchmark as a reference point, this paper enables us to grasp the financial health of the private Indian airports. Besides answering the critical questions about a tradeoff between investment towards expansion and economic feasibility, this paper analyzes the unaudited financial reports over a span of five years to study the feasibility of listing these Indian airports on the Indian stock exchange. Thereby, the paper explores stock listing of airports as an alternative mode to finance airport expansion to cater to the exponential growth forecasted in the coming future.