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This paper presents the development of CMP process optimization in order to obtain very good bondability of tungsten wafers. Surface quality of polished tungsten wafers under different conditions is analyzed through statistical tools like standard deviation, skewness and kurtosis. Good surface quality for planarized wafers is obtained by polishing under optimized conditions process, allowing highly improved bonding quality, as shown by Scanning Acoustic Microscopy.

Beyond C14nm, better W CMP performances are required due to new CMOS integration constraints such as contact density increase, wide W feature introduction or low oxide loss for any polishing steps related to gate building. In order to address these new requirements, this paper propose an approach similar to Cu damascene CMP, using three consecutive polishing steps respectively for planarization, selective stop on Ti/TiN barrier and barrier removal. This study discuss advantages and limitations of this approach and points out process improvement obtained among which lower oxide erosion, tunable W recess, better oxide WIWNU and minimized oxide loss.

We demonstrate the feasibility of producing advanced silicon photonic devices for future data communication nodes at 40Gbps using CMOS compatible processes in a 300mm wafer fab. Basic building blocks are shown together with various wavelength division multiplexing solutions. All the devices presented are integrated on 220nm SOI or locally grown epitaxial germanium.

Monolithic 3D Integration (3DMI) consists in processing transistors on top of each other sequentially. This technology appears to be an alternative solution to scaling, from the 7nm node integration and below, as substantial gain in area and performance as compared to planar technology is expected without scaling the transistor technology node. 3DMI appears to be the most optimized way to take advantage of the vertical dimension as almost no alignment constraints remains. By using a standard lithography, the top transistors can be aligned directly onto their bottom counterparts with a high accuracy (see Fig. 1), contrary to TSV-based 3D technologies [2]. Furthermore, 3DMI is a highly versatile technology as the different transistor levels can be optimized independently, from the choice of the channel characteristics (e.g. material, orientation, strain) to the architecture itself (e.g. CMOS on CMOS, PMOS on NMOS, FinFET on BULK, LVT on RVT) [3]. Such sequential integration raises two main technological challenges: - Creating an active layer above a bottom transistor which will become the channel of the top transistor. In order to achieve similar performance for top FET than bottom FET, the substrate quality must be equivalent than commercial substrates. Thus, this layer must be monocristalline and defect free in order to optimize the mobility and to be consistent with high performance criteria. A precise thickness control is also necessary in order to avoid device performance dispersion. - Realizing a high performance top transistor level without degrading the bottom level as the stacked transistor levels are processed sequentially, i.e. at low temperature process –typically below 600°C. Recent results demonstrate some integration solutions, such as junction activation by Solid Phase Epitaxy Regrowth below 600°C [4]. To tackle the first challenge, we transfer a thin silicon layer from a high quality Silicon On Insulator (SOI) wafer by direct bonding. It appears to be the most effective solution to obtain a defect free monocristalline active layer with a well-controlled thickness. This method is preferred to different techniques which have been developed to create large monocristal grains of silicon either by laser anneal of amorphous Poly-Silicon [5] or by µ-Czochralsky process [6]. However, in both cases, large “seed layers” are necessary to control the orientation and the size of these grains, which is not consistent with for high density circuits. For this layer transfer, a blanket SOI wafer on which a Si02 layer is either grown or deposited, is bonded on the classical pre-metal dielectric above the bottom transistor level. The SOI backside is then removed by grinding and chemical etching to keep only the silicon layer. While expert knowledge has been reached for full sheet wafer bonding, the situation on a patterned layer can be really challenging with the design rules of 3DMI. In order to face these challenges, the surface preparation, the direct bonding process and the thinning steps have been optimized to prevent any defect on the whole 300mm surface. Also TMAH bevel edge protection and silicide protection layer have been added. This work will give a general overview of 3D monolithic challenges. Also, a specific focus will be made on direct bonding which is a major enabler of this type of integration. Indeed among the other alternative techniques, it appears to be the best solution to meet the high performance and high density criteria. REFERENCES: [1] P. Batude et al., VLSI Technology, pp. 158 (2011) [1] P. Batude et al., ECS Spring meeting, (16) pp. 47 (2008) [2] P. Batude et al., IITC-AMC (2014) [3] P. Batude et al., IEDM, pp.731-734 (2011) [4] C-H. Shen et al., IEDM, pp. 931-934 (2013) [5] J. Derakhshandeh et al., TED vol.58, no. 11 (2011) Fig.1: 3DMI demonstration with ultra-high alignment between the stacked transistors [1] obtained with 248nm stepper.