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IntroductionThe field of machine learning has undergone a significant transformation with the progress of deep artificial neural networks (ANNs) and the growing accessibility of annotated data. ANNs usually require substantial power and memory usage to achieve optimal performance. Spiking neural networks (SNNs) have recently emerged as a low-power alternative to ANNs due to their sparsity nature. Despite their energy efficiency, SNNs are generally more difficult to be trained than ANNs.MethodsIn this study, we propose a novel three-stage SNN training scheme designed specifically for segmenting human hippocampi from magnetic resonance images. Our training pipeline starts with optimizing an ANN to its maximum capacity, then employs a quick ANN-SNN conversion to initialize the corresponding spiking network. This is followed by spike-based backpropagation to fine-tune the converted SNN. In order to understand the reason behind performance decline in the converted SNNs, we conduct a set of experiments to investigate the output scaling issue. Furthermore, we explore the impact of binary and ternary representations in SNN networks and conduct an empirical evaluation of their performance through image classification and segmentation tasks.Results and discussionBy employing our hybrid training scheme, we observe significant advantages over both ANN-SNN conversion and direct SNN training solutions in terms of segmentation accuracy and training efficiency. Experimental results demonstrate the effectiveness of our model in achieving our design goals.

A comprehensive simulation study has been conducted to show fine-grain reconfigurability in CMOS circuits using work-function engineering (WFE) on Schottky barrier (SB) FinFETs for sub-10-nm gate length. The study has three subsections. First, two-transistor (2T) and 4T and-or-invert (AOI)/or-and-invert (OAI) gates with select bits that allow multiple logic functions are introduced. Second, the use of WFE to create ultracompact reconfigurable logic circuits of fundamental operations (0, 1, OR, AND, NAND, NOR, and XOR) are explored via novel 2T, 3T, and 4T gates. These circuits include one or two select bits that are capable of commanding up to four functions with two inputs. To further illustrate the potential of WFE for reconfigurable logic, novel multistage circuits, such as compact full adders, are also modeled via TCAD simulations. Power $\times $ delay product (PDP) figures and dc gain of the proposed gates are quantified and compared against the CMOS designs with similar functionality. Finally, we also design a novel compact 1-bit arithmetic logic unit (ALU), which has seven exclusive logic operations (1, NAND, OR, XOR, NOR, addition, and subtraction) with three select bits using only 26 SB-FinFETs, saving a substantial amount of power and chip area. The tradeoffs between the number of metal work-functions used in the designs, circuit complexity, and simulated performance metrics are also provided. The comparative simulations between reconfigurable SB-FinFET-based designs versus conventional p-n junction FinFET circuits show that WFE can lead to absolutely minimalist reconfigurable CMOS logic blocks using $\times 3$ to $\times 10$ less power and between $\times 2$ and $\times 15$ less area than static CMOS counterparts. Although they suffer greater delays ( $\times 2$ – $\times 5$ ), the overall PDP performance remains comparable to conventional CMOS.

An extensive analysis of sub-10-nm logic building blocks utilizing ultracompact logic gates based on recently proposed gate workfunction engineering (WFE) approach is provided. WFE sets the WF in the contacts as well as two independent gates of an ambipolar Schottky-barrier (SB) FinFET to alter the threshold of two channels, as a unique leverage to modify the logic functionality out of a single transistor. Thus, a single transistor (1T) CMOS pass-gate, 2T NAND and NOR gates as well as 3T or 4T XOR gates with substantial reduction in overall area (50%) and power (up to ×10$ ) dissipation can be implemented. To harness this potential and illustrate the capabilities of these compact ambipolar transistors, novel logic building blocks, including 6T multiplexer, 8T full-adder, 4T latch, 6T D-type flip-flop, and 4T AND-OR-invert (AOI) gates, are developed. Besides the logic verification using 7-nm devices, the dynamic performance of the proposed logic circuits is also analyzed. The comparative simulation study shows that WFE in independent-gate SB-FinFETs can lead to absolutely minimalist CMOS logic blocks without significant degradation to overall power-delay product (PDP) performance.