Search

Moving from monolithic scaling to the second (2D) and to the third dimension (3D) is becoming increasingly important within industry. In the last years heterogeneous and chiplet integration, utilizing advanced packaging technologies, has increased in complexity as well as in variability. Higher performance, wider bandwidth and lower power consumption and space requirements drive the approach toward 3D integration, whereas the need of finer RDL line/spacing as well as smaller μ-bumps and μ-pillars critical dimension tighten integration design rules at the package and substrate level. Individual chiplet's I/O bumps and interconnects pitch scaling nowadays moves towards 2/2μm L/S. Although the flexible re-integration of larger dies from smaller chiplets, from various technology nodes to partitioned dies has shown numerous advantages over monolithic SoC technologies with larger freedom of design, this approach shifts the complexity into the integration and with it into the lithographic patterning processes. In this work a profound evaluation of common advanced packaging high resolution, thin and thick resists for RDL & μ-bump/μ-pillar manufacturing is presented, utilizing maskless exposure to demonstrate its patterning performance. Resolution tests, focal position & exposure matrices, including resist sidewall profiles are discussed in view of the 2/2μm L/S requirements for heterogeneous integration. Furthermore, the high-speed digital processing meets the needs for design flexibility and scalability for a wide range of packaging technologies by enabling both, die- and wafer-level designs, fast tape-out changes together with sub-μm adaptability.

CMOS image sensors technology is nowadays widely used in various applications due to multiple advantages, such as low cost, low power consumption, on chip functionality, high-speed of operation [1]. The market for CMOS image sensor (CIS) technology is continuously growing, as this technology is key technology in the most of the main electronic megatrends, such as smart automotive, portable & mobile electronics, novel human machine interfaces for AR/ VR devices, 3D sensing or $\mu$ -displays and advanced healthcare requirements. In order to follow and continue CIS scaling for thinner and smaller devices, an adoption of new processes and materials is required. Mainly improving optical performance as well as imagining characteristics of image sensors, such as higher image resolution, better contrast and desired optical density of the colored resist materials are key aspects of today's development.

Adhesive bonding using an ultra-thin polymer layer is getting more attention for more than Moore applications. However some challenges of ultra-thin layer coating remain and are subject to further research. For this purpose diluted BCB adhesive layers were evaluated to create bonding layers down to 30 nm adhesive thickness. BCB is a well-known and thus favourable candidate for this evaluation due to it’s physical properties, such as low curing temperature, high degree of planarization, high optical clarity, along with good compatibility with various metallization systems.