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In this work, approximate eight-bit floating-point operations performed using simple integer operations is discussed. For two-bit mantissa formats, faithful rounding can always be obtained for the considered operations. For all operations, correctly rounded results can be obtained for different rounding modes, either directly or by adding a conditional carry in. For three-bit mantissa formats, faithful rounding can be sometimes be obtained directly, while for other operations a conditional carry in must be added. Correctly rounded results can be obtained for most operations and rounding modes using slightly more complicated expressions for the carry in. Hardware implementation results for multiplication using both standard cell and FPGA technology are presented illustrating the potential benefit of integer computation. Especially for FPGA, significant resource savings are obtained., Comment: Submitted to IEEE Symposium on Computer Arithmetic on Feb. 12 2024

The main object of this paper is to study the generalized von mangoldt function using the L-additive function, which can help us give many result about the classical arithmetic function., Comment: 14 pages

Let $[x]$ be the integral part of $x$, $n>1$ be a positive integer and $\chi_n$ denote the trivial Dirichlet character modulo $n$. In this paper, we use an identity established by Z. H. Sun to get congruences of $T_{m,k}(n)=\sum_{x=1}^{[n/m]}\frac{\chi_n(x)}{x^k}\left(\bmod n^{r+1}\right)$ for $r\in \{1,2\}$, any positive integer $m $ with $n \equiv \pm 1 \left(\bmod m \right)$ in terms of Bernoulli polynomials. As its an application, we also obtain some new congruences involving binomial coefficients modulo $n^4$ in terms of generalized Bernoulli numbers., Comment: 21pages

In this work, we study a quasilinear elliptic problem involving the 1-laplacian operator, with a discontinuous, superlinear and subcritical nonlinearity involving the Heaviside function $H(\cdot - \beta)$. Our approach is based on an analysis of the associated p-laplacian problem, followed by a thorough analysis of the asymptotic behaviour or such solutions as $p \to 1^+$. We study also the asymptotic behaviour of the solutions, as $\beta \to 0^+$ and we prove that it converges to a solution of the original problem, without the discontinuity in the nonlinearity., Comment: 21 pages

Processing-in-memory (PIM), an increasingly studied neuromorphic hardware, promises orders of energy and throughput improvements for deep learning inference. Leveraging the massively parallel and efficient analog computing inside memories, PIM circumvents the bottlenecks of data movements in conventional digital hardware. However, an extra quantization step (i.e. PIM quantization), typically with limited resolution due to hardware constraints, is required to convert the analog computing results into digital domain. Meanwhile, non-ideal effects extensively exist in PIM quantization because of the imperfect analog-to-digital interface, which further compromises the inference accuracy. In this paper, we propose a method for training quantized networks to incorporate PIM quantization, which is ubiquitous to all PIM systems. Specifically, we propose a PIM quantization aware training (PIM-QAT) algorithm, and introduce rescaling techniques during backward and forward propagation by analyzing the training dynamics to facilitate training convergence. We also propose two techniques, namely batch normalization (BN) calibration and adjusted precision training, to suppress the adverse effects of non-ideal linearity and stochastic thermal noise involved in real PIM chips. Our method is validated on three mainstream PIM decomposition schemes, and physically on a prototype chip. Comparing with directly deploying conventionally trained quantized model on PIM systems, which does not take into account this extra quantization step and thus fails, our method provides significant improvement. It also achieves comparable inference accuracy on PIM systems as that of conventionally quantized models on digital hardware, across CIFAR10 and CIFAR100 datasets using various network depths for the most popular network topology., Comment: 25 pages, 12 figures, 8 tables

Neuromorphic computers perform computations by emulating the human brain, and use extremely low power. They are expected to be indispensable for energy-efficient computing in the future. While they are primarily used in spiking neural network-based machine learning applications, neuromorphic computers are known to be Turing-complete, and thus, capable of general-purpose computation. However, to fully realize their potential for general-purpose, energy-efficient computing, it is important to devise efficient mechanisms for encoding numbers. Current encoding approaches have limited applicability and may not be suitable for general-purpose computation. In this paper, we present the virtual neuron as an encoding mechanism for integers and rational numbers. We evaluate the performance of the virtual neuron on physical and simulated neuromorphic hardware and show that it can perform an addition operation using 23 nJ of energy on average using a mixed-signal memristor-based neuromorphic processor. We also demonstrate its utility by using it in some of the mu-recursive functions, which are the building blocks of general-purpose computation.

We give necessary and sufficient conditions for the boundedness of the maximal commutators $M_{b}$, the commutators of the maximal operator $[b, M]$ and the commutators of the sharp maximal operator $[b, M^{\sharp}]$ in Orlicz spaces $L^{\Phi}(\mathbb{G})$ on any stratified Lie group $\mathbb{G}$ when $b$ belongs to Lipschitz spaces $\dot{\Lambda}_{\beta}(\mathbb{G})$. We obtain some new characterizations for certain subclasses of Lipschitz spaces $\dot{\Lambda}_{\beta}(\mathbb{G})$., Comment: AMS-LaTeX 22 pages. arXiv admin note: text overlap with arXiv:1803.03069

Neuronal network computation and computation by avalanche supporting networks are of interest to the fields of physics, computer science (computation theory as well as statistical or machine learning) and neuroscience. Here we show that computation of complex Boolean functions arises spontaneously in threshold networks as a function of connectivity and antagonism (inhibition), computed by logic automata (motifs) in the form of computational cascades. We explain the emergent inverse relationship between the computational complexity of the motifs and their rank-ordering by function probabilities due to motifs, and its relationship to symmetry in function space. We also show that the optimal fraction of inhibition observed here supports results in computational neuroscience, relating to optimal information processing., Comment: 11 pages, 7 figures, 1 table, includes supplementary information

Stochastic computing (SC) is a low-cost computational paradigm that has promising applications in digital filter design, image processing and neural networks. Fundamental to these applications is the weighted addition operation which is most often implemented by a multiplexer (mux) tree. Mux-based adders have very low area but typically require long bit-streams to reach practical accuracy thresholds when the number of summands is large. In this work, we first identify the main contributors to mux adder error. We then demonstrate with analysis and experiment that two new techniques, precise sampling and full correlation, can target and mitigate these error sources. Implementing these techniques in hardware leads to the design of CeMux (Correlation-enhanced Multiplexer), a stochastic mux adder that is significantly more accurate and uses much less area than traditional weighted adders. We compare CeMux to other SC and hybrid designs for an electrocardiogram filtering case study that employs a large digital filter. One major result is that CeMux is shown to be accurate even for large input sizes. CeMux's higher accuracy leads to a latency reduction of 4x to 16x over other designs. Further, CeMux uses about 35% less area than existing designs, and we demonstrate that a small amount of accuracy can be traded for a further 50% reduction in area. Finally, we compare CeMux to a conventional binary design and we show that CeMux can achieve a 50 to 73% area reduction for similar power and latency as the conventional design, but at a slightly higher level of error.

Let $q>2$ be an odd integer. For each integer $x$ with $0

Stochastic computing has a long history as an alternative method of performing arithmetic on a computer. While it can be considered an unbiased estimator of real numbers, it has a variance and MSE on the order of $\Omega(\frac{1}{N})$. On the other hand, deterministic variants of stochastic computing remove the stochastic aspect, but cannot approximate arbitrary real numbers with arbitrary precision and are biased estimators. However, they have an asymptotically superior MSE on the order of $O(\frac{1}{N^2})$. Recent results in deep learning with stochastic rounding suggest that the bias in the rounding can degrade performance. We proposed an alternative framework, called dither computing, that combines aspects of stochastic computing and its deterministic variants and that can perform computing with similar efficiency, is unbiased, and with a variance and MSE also on the optimal order of $\Theta(\frac{1}{N^2})$. We also show that it can be beneficial in stochastic rounding applications as well. We provide implementation details and give experimental results to comparatively show the benefits of the proposed scheme., Comment: 8 pages, 16 figures, 1 table

Finite field multiplier is mainly used in error-correcting codes and signal processing. Finite field multiplier is regarded as the bottleneck arithmetic unit for such applications and it is the most complicated operation over finite field GF(2m) which requires a huge amount of logic resources. In this paper, a new modified serial-in parallel-out multiplication algorithm with interleaved modular reduction is suggested. The proposed method offers efficient area architecture as compared to proposed algorithms in the literature. The reduced finite field multiplier complexity is achieved by means of utilizing logic NAND gate in a particular architecture. The efficiency of the proposed architecture is evaluated based on criteria such as time (latency, critical path) and space (gate-latch number) complexity. A detailed comparative analysis indicates that, the proposed finite field multiplier based on logic NAND gate outperforms previously known results, Comment: The simulation results needs to be to verified

This paper proposes a brain-inspired approach to quantum machine learning with the goal of circumventing many of the complications of other approaches. The fact that quantum processes are unitary presents both opportunities and challenges. A principal opportunity is that a large number of computations can be carried out in parallel in linear superposition, that is, quantum parallelism. The challenge is that the process is linear, and most approaches to machine learning depend significantly on nonlinear processes. Fortunately, the situation is not hopeless, for we know that nonlinear processes can be embedded in unitary processes, as is familiar from the circuit model of quantum computation. This paper explores an approach to the quantum implementation of machine learning involving nonlinear functions operating on information represented topographically (by computational maps), as common in neural cortex., Comment: 29 pages

In this paper we consider the matrix structure of arithmetic processors based on distributed arithmetic in multi-row codes. Scope - development of supercomputers., Comment: 22pages (russian-original) + 19 pages(english-robotic translationn)

This report covers an intelligent decision support system (IDSS), which handles an efficient and effective way to rapidly inspect containerized cargos for defection. Defection is either cargo exposure to radiation, physical damages such as holes, punctured surfaces, iron surface oxidation, etc. The system uses a sorting array triangulation technique (SAT) and surface damage detection (SDD) to conduct the inspection. This new technique saves time and money on finding damaged goods during transportation such that, instead of running $n$ inspections on $n$ containers, only 3 inspections per triangulation or a ratio of $3:n$ is required, assuming $n > 3$ containers. The damaged stack in the array is virtually detected contiguous to an actually-damaged cargo by calculating nearby distances of such cargos, delivering reliable estimates for the whole local stack population. The estimated values on damaged, somewhat damaged and undamaged cargo stacks, are listed and profiled after being sorted by the program, thereby submitted to the manager for a final decision. The report describes the problem domain and the implementation of the simulator prototype, showing how the system operates via software, hardware with/without human agents, conducting real-time inspections and management per se., Comment: This article is a report on a developed IDSS system/prototype aimed to be published for a journal conference proceedings and/or a full paper under Computer Science and Software Engineering categories. 28 pages; 10 Figures including graphs; 5 tables; presentation file is available at http://web.uvic.ca/~phibal12/Presentations/IDSS_proj.pptx Ask authors for full code and/or other files

This article is about the architecture of a lossless wavelet filter bank with reprogrammable logic. It is based on second generation of wavelets with a reduced of number of operations. A new basic structure for parallel architecture and modules to forward and backward integer discrete wavelet transform is proposed., Comment: 7 pages, The ACM proceedings of CompSysTech 2003