115 results on '"Baeg, Sanghyeon"'
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2. FBGA solder ball defect effect on DDR4 data signal rise time and ISI measured by loading the data line with a capacitor
3. Correctable and uncorrectable errors using large scale DRAM DIMMs in replacement network servers
4. Failure signature analysis of power-opens in DDR3 SDRAMs
5. Signal characteristic and test exploitation for intermittent nanometer-scale cracks
6. Study of proton radiation effect to row hammer fault in DDR4 SDRAMs
7. Write Recovery Time Degradation by Thermal Neutrons in DDR4 DRAM Components
8. Temporal and frequency characteristic analysis of margin-related failures caused by an intermittent nano-scale fracture of the solder ball in a BGA package device
9. An alternative approach to measure alpha-particle-induced SEU cross-section for flip-chip packaged SRAM devices: High energy alpha backside irradiation
10. Statistical distributions of row-hammering induced failures in DDR3 components
11. DDR4 Ball Grid Array package intermittent fracture effect on signal integrity
12. Temperature Estimation of HBM2 Channels with Tail Distribution of Retention Errors in FPGA-HBM2 Platform
13. Experiments and root cause analysis for active-precharge hammering fault in DDR3 SDRAM under 3 × nm technology
14. Quantification of Substrate Current Caused by an Individual Trap at Different Locations and Energies, Prevailing on Si/SiO₂ Interface or Si Substrate of n-MOSFETs
15. Soft error tolerant Content Addressable Memories (CAMs) using error detection codes and duplication
16. Estimation of the Trap Energy Characteristics of Row Hammer-Affected Cells in Gamma-Irradiated DDR4 DRAM
17. Divulge of Root Cause Failure in Individual Cells of 2x nm Technology DDR4 DRAM at Operating Temperature
18. Characterization of Si Charged Particles Detector by Measurement and Analysis of its Dark Current
19. DDR4 BER Degradation Due to Crack in FBGA Package Solder Ball
20. Comparative study of MC-50 and ANITA neutron beams by using 55 nm SRAM
21. Protection of memories suffering MCUs through the selection of the optimal interleaving distance
22. SRAM interleaving distance selection with a soft error failure model
23. Null detector circuit design scheme for detecting defective AC-coupled capacitors in differential signaling
24. Fault Coverage Re-Evaluation of Memory Test Algorithms With Physical Memory Characteristics
25. Exploitations of Multiple Rows Hammering and Retention Time Interactions in DRAM Using X-Ray Radiation
26. DDR4 Data Channel Failure Due to DC Offset Caused by Intermittent Solder Ball Fracture in FBGA Package
27. A theoretical and experimental investigation of Bragg's rule for energy-loss straggling in low mean energy loss regime in air and its constituents
28. Low-power ternary content-addressable memory design using a segmented match line
29. Failure Analysis of Galaxy S7 Edge Smartphone Using Neutron Radiation
30. Experimental Exploitation of Random and Deterministic Data Patterns for Stringent DDR4 I/O Timing Margins
31. Architectural design tradeoffs in SRAM-based TCAMs
32. Study of TID effects on one row hammering using gamma in DDR4 SDRAMs
33. Soft error study on DDR4 SDRAMs using a 480 MeV proton beam
34. Resource-Efficient SRAM-Based Ternary Content Addressable Memory
35. Active Precharge Hammering to Monitor Displacement Damage Using High-Energy Protons in 3x-nm SDRAM
36. Erratum: Assessing alpha-particle-induced SEU sensitivity of flip-chip bonded SRAM using high energy irradiation [IEICE Electronics Express Vol. 13 (2016) No. 17 pp. 20160627]
37. Logic soft error study with 800-MHz DDR3 SDRAMs in 3x nm using proton and neutron beams
38. Stuck Bits Study in DDR3 SDRAMs Using 45-MeV Proton Beam
39. Active-precharge hammering on a row induced failure in DDR3 SDRAMs under 3× nm technology
40. Novel Error Detection Scheme With the Harmonious Use of Parity Codes, Well-Taps, and Interleaving Distance
41. An Efficient Multiple Cell Upsets Tolerant Content-Addressable Memory
42. Characterizing the Capacitive Crosstalk in SRAM Cells Using Negative Bit-Line Voltage Stress
43. Soft Error Issues with Scaling Technologies
44. Vertically Partitioned SRAM-Based Ternary Content Addressable Memory
45. Memory Reliability Model for Accumulated and Clustered Soft Errors
46. Mitigating the effects of large multiple cell upsets (MCUs) in memories
47. DRAM failure cases under hot-carrier injection
48. Designing ad-hoc scrubbing sequences to improve memory reliability against soft errors
49. AC-DC factor sensitivity for DRAM components lifetime under hot-carrier injection
50. Multiple cell upsets tolerant content-addressable memory
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