15 results on '"Bahn, Jun Ho"'
Search Results
2. Self-optimized Routing in a Network on-a-Chip
3. A Generic Network Interface Architecture for a Networked Processor Array (NePA)
4. Efficient Parallel Buffer Structure and Its Management Scheme for a Robust Network-on-Chip (NoC) Architecture
5. Self-optimized Routing in a Network on-a-Chip
6. A Generic Network Interface Architecture for a Networked Processor Array (NePA)
7. Parallel processing for block ciphers on a fault tolerant networked processor array
8. Parallel LDPC Decoding on a Network-on-Chip Based Multiprocessor Platform
9. PARALLEL FFT ALGORITHMS ON NETWORK-ON-CHIPS
10. Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip
11. ON DESIGN AND APPLICATION MAPPING OF A NETWORK-ON-CHIP(NOC) ARCHITECTURE
12. Parallel FFT Algorithms on Network-on-Chips
13. Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)
14. On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture
15. Design of a router for network-on-chip
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.