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In recent days, more hardware-driven artificial intelligence system capable of brain-like low-energy consumption is gaining ever-increasing interest. The hardware-driven property lies in the low-power synaptic device and its array along with the area and energy-efficient neuron circuits. In this work, a spiking neural network (SNN) based on analog synaptic device of resistive-switching random access memory (RRAM) is constructed from the experimentally fabricated devices. Furthermore, the capability of the designed SNN hardware for sequential tasks through an optimal reinforcement learning (RL) algorithm is demonstrated. More specifically, the Rush Hour game is conducted as an example of applications for the sequential task for which an SNN architecture is plausibly suited. The rule of the game is simple but has not been demonstrated by a hardware-oriented artificial neural network (ANN) yet, and in this work, it is reported that the analog RRAM synaptic devices in the cross-point array architecture successfully solve the problem via the RL algorithm. [ABSTRACT FROM AUTHOR]

Experiments are conducted to compare the resistive switching characteristics for several samples with different amounts of Ag deposition in TiN/Ag/SiNx/TiN conductive bridging random access memory (CBRAM). The compliance current in TiN/Ag/SiNx/TiN CBRAM determines the volatile/non-volatile memory operation as the current level controls the strength of the filament made of Ag. The transient measurement showed that the effective thickness of Ag source layer in the TiN/Ag/SiNx/TiN controls the supply of the Ag atoms into the insulating layer, affecting the strength of the conductive bridge. The mechanism for the switching characteristics and the volatility trend with the amount of Ag deposition is closely investigated using transmission electron microscopy and scanning electron microscopy images. The device shows the conductance potentiation by a voltage pulse train under 1 µA current level, and the higher potentiation rate is observed in the CBRAM with thick Ag source layer. [ABSTRACT FROM AUTHOR]

We fabricated a silicon based nano-wedge resistive switching memory device with the stack of Ti/HfOx/p+-Si. By using 25% tetra-methyl-ammonium hydroxide (TMAH) aqueous solution, the anisotropic wet etching process is carried out to minimize the tip structure of the silicon bottom electrode to a width of 4 nm, and the structure was validated through TEM analysis. Due to the minimized device area, low read current levels (<1 μA) were obtained in the nano-wedge RRAM while the opposites were measured in large size RRAM devices. In addition, the fabricated nano-wedge RRAM exhibited low power consumption during the DC switching process. Additionally, pulse measurement and retention tests were performed to demonstrate the synaptic behaviors of long-term potentiation and depression. Software neural network simulation was followed to test the feasibility of nano-wedge RRAM's array implementation. These results demonstrate the fabricated nano-wedge RRAM devices' potential usage as a synaptic device in neuromorphic computing systems. [ABSTRACT FROM AUTHOR]

In this article, we report a method for recovering a resistive-switching random access memory (RRAM) from the reset breakdown and enhancing the endurance characteristics. A SiNx-based RRAM device has been fabricated and its switching characteristics are analyzed with a particular interest in reset breakdown. It has been found that the SiNx RRAM in permanent reset breakdown can be revived to high-resistance state (HRS) by thermal recovery, a low-temperature annealing method. The memory window could be widened even with enhanced reset stability and conductance distribution. Temperature-dependent conductance change has been measured in order to figure out the substantial component of conductive filament and the mechanism of thermal recovery. The experimental evidences show that the reset breakdown process is the result of unwanted Si dangling bond (Si-DB) formation. By thermal recovery, Ni filament could be ruptured without applying a high electric field which induces negative set. [ABSTRACT FROM AUTHOR]

In this letter, we demonstrated improved resistive switching (RS) characteristics for a complementary metal-oxide-semiconductor compatible Ni/Ti/Al2O3/SiO2/Si device structure. The robust SiO2 layer deposited by the additional low-pressure chemical vapor deposition process can improve the RS characteristics such as the endurance cycle, current level, and on/off ratio. Moreover, the multilevel capability is enhanced in the bilayer structure; the larger the reset stop voltage, the greater the on/off ratio demonstrated. Furthermore, for practical RS operation, several resistance states were obtained by adjusting the pulse amplitude. This property is desirable for highly integrated nonvolatile memory applications. [ABSTRACT FROM AUTHOR]

In this paper, we have investigated the effect of additional thin SiO2 layer on switching variability of SiNx-based resistive memory (RRAM). We found that excessive LRS state generated in set operation results in large reset current and abrupt reset operation. The abrupt reset operation leads to large distribution of HRS. To investigate the transient characteristics of switching procedure in detail, measurement environment was implemented with equivalent circuit, and measured current from equipment was separated into capacitive and resistive current of resistive memory cell. Consequently, we point the internal overshoot current occurring in set operation as the cause of the excessive leaky state leading to large resistance distributions. Finally, we confirm the effect of low resistance state value ( $R_{{\text{LRS}}}$ ) and cell capacitance ( $C_{{\text{DUT}}}$ ) on the internal overshoot current of RRAM. [ABSTRACT FROM AUTHOR]

Here we demonstrate low-power resistive switching in a Ni/SiNy/SiNx/p++-Si device by proposing a double-layered structure (SiNy/SiNx), where the two SiN layers have different trap densities. The LRS was measured to be as low as 1 nA at a voltage of 1 V, because the SiNx layer maintains insulating properties for the LRS. The single-layered device suffers from uncontrollability of the conducting path, accompanied by the inherent randomness of switching parameters, weak immunity to breakdown during the reset process, and a high operating current. On the other hand, for a double-layered device, the effective conducting path in each layer, which can determine the operating current, can be well controlled by the ICC during the initial forming and set processes. A one-step forming and progressive reset process is observed for a low-power mode, which differs from the high-power switching mode that shows a two-step forming and reset process. Moreover, nonlinear behavior in the LRS, whose origin can be attributed to the P–F conduction and F–N tunneling driven by abundant traps in the silicon-rich SiNx layer, would be beneficial for next-generation nonvolatile memory applications by using a conventional passive SiNx layer as an active dielectric. [ABSTRACT FROM AUTHOR]

Here we demonstrate low-power resistive switching in a Ni/SiN y /SiN x /p ++ -Si device by proposing a double-layered structure (SiN y /SiN x ), where the two SiN layers have different trap densities. The LRS was measured to be as low as 1 nA at a voltage of 1 V, because the SiN x layer maintains insulating properties for the LRS. The single-layered device suffers from uncontrollability of the conducting path, accompanied by the inherent randomness of switching parameters, weak immunity to breakdown during the reset process, and a high operating current. On the other hand, for a double-layered device, the effective conducting path in each layer, which can determine the operating current, can be well controlled by the I CC during the initial forming and set processes. A one-step forming and progressive reset process is observed for a low-power mode, which differs from the high-power switching mode that shows a two-step forming and reset process. Moreover, nonlinear behavior in the LRS, whose origin can be attributed to the P-F conduction and F-N tunneling driven by abundant traps in the silicon-rich SiN x layer, would be beneficial for next-generation nonvolatile memory applications by using a conventional passive SiN x layer as an active dielectric.

SiN x -based nano-structure resistive memory is fabricated by fully silicon CMOS compatible process integration including particularly designed anisotropic etching for the construction of a nano-cone silicon bottom electrode (BE). Bipolar resistive switching characteristics have significantly reduced switching current and voltage and are demonstrated in a nano-cone BE structure, as compared with those in a flat BE one. We have verified by systematic device simulations that the main cause of reduction in the performance parameters is the high electric field being more effectively concentrated at the tip of the cone-shaped BE. The greatly improved nonlinearity of the nano-cone resistive memory cell will be beneficial in the ultra-high-density crossbar array.